PCI-MT32-O4-N2 Lattice, PCI-MT32-O4-N2 Datasheet - Page 114

• Manufacturer Part Number: PCI-MT32-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-44. 32-bit Target Burst Write Transaction With a 64-bit Local Interface
CLK
1
2
3
4
5
6
7
PCI Data
Address
Phase
Data 1
Data 2
Data 3
Wait
Wait
Wait
The master asserts framen and drives ad[31:0] and cben[3:0].
The PCI master drives the first byte enable (Byte Enable 1) on cben[3:0]. If it is ready to write
data, it asserts irdyn and drives the first DWORD (Data 1) on ad[31:0].The Core starts to
decode the address and command. It drives the lt_address_out to the back-end.
If there is an address match, the Core drives the bar_hit signals to the back-end application.
The back-end can use bar_hit as a chip select.
If the DEVSEL_TIMING is set to slow, the Core asserts devseln on the clock after bar_hit. If
the back-end will be ready to write data in two cycles, it can assert lt_rdyn.
trdyn is asserted since lt_rdyn was asserted the previous cycle.
Quad Word Aligned
The Core keeps trdyn asserted and puts Data 1 on the lower DWORD of lt_data_out.
If both irdyn and trdyn are asserted on the previous cycle, the master drives the next byte
enable (Byte Enable 2) on cben[3:0]. If the PCI master is still ready to write data, it keeps
irdyn asserted and drives the next DWORD (Data 2) on ad[31:0].
If both irdyn and trdyn were asserted on the previous cycle, the Core asserts
lt_ldata_xfern to the back-end to signify that Data 1 is valid. With lt_ldata_xfern
asserted, the back-end doesn’t write the data or increment the address counter.
Double Word Aligned
The Core keeps trdyn asserted and puts Data 1 on the upper DWORD of lt_data_out.
If both irdyn and trdyn are asserted on the previous cycle, the master drives the next byte
enables (Byte Enable 2) on cben[3:0]. If the master is still ready to write data, it keeps irdyn
asserted and drives the next DWORD (Data 2) on ad[31:0].
If irdyn, trdyn and lt_rdyn are asserted on the previous cycle, the Core asserts
lt_hdata_xfern to the back-end to signify that Data 1 is valid. With lt_hdata_xfern
asserted, the back-end can safely write the QWORD (Don’t care and Data 1) and increment the
address counter.
Quad Word Aligned
The back-end puts Data 2 on lt_data_out. If the back-end keeps lt_rdyn asserted on the pre-
vious cycle, the Core keeps trdyn asserted.
If both irdyn and trdyn are asserted on the previous cycle, the master drives the next byte
enables (Byte Enable 3) on cben[3:0]. If the master is still ready to write data, it keeps irdyn
asserted and drives the next DWORD (Data 3) on ad[31:0]. The master signals the end of the
burst when it de-asserts framen.
The Core de-asserts lt_ldata_xfern. If irdyn, trdyn and lt_rdyn are asserted on the pre-
vious cycle, the Core asserts lt_hdata_xfern to the back-end to signify that Data 2 is valid.
With lt_hdata_xfern asserted, the back-end can safely write the QWORD (Data 1 and Data 2)
and increment the address counter.
Double Word Aligned
The Core keeps trdyn asserted and puts Data 2 on lt_data_out.
If both irdyn and trdyn are asserted on the previous cycle, the master drives the next byte
enables (Byte Enable 3) on cben[3:0]. If the master is still ready to write data, it keeps irdyn
asserted and drives the next DWORD (Data 3) on ad. The master signals the end of the burst
when it de-asserts framen.
The Core de-asserts lt_hdata_xfern. If both irdyn and trdyn are asserted on the previous
cycle, the Core asserts lt_ldata_xfern to the back-end to signify Data 2 is valid. With
lt_ldata_xfern asserted, the back-end doesn’t write the data or increment the address coun-
ter.
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Description
Functional Description
PCI IP Core User’s Guide