PCI-MT32-O4-N2 Lattice, PCI-MT32-O4-N2 Datasheet - Page 46

• Manufacturer Part Number: PCI-MT32-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
Functional Description
Configuration Read and Write Transactions
When operating as a PCI master, the PCI IP core supports Configuration cycles to CSR addresses 00h to FFh.
The Local Master Interface has full control of these types of accesses, which are similar to the memory transac-
tions described in earlier sections. The PCI IP core only supports 32-bit, single data phase transactions to the con-
figuration registers.
During a configuration access, the PCI master drives an address/data pin that is connected to the idsel signal for
all of the PCI target devices. For more information on the binding of the address/data signals to the idsel signal,
refer to the PCI Local Bus Specification, Revision 3.0.
PCI Master I/O Read and Write Transactions
The PCI IP core’s application executes I/O space transactions. Transactions to I/O address space are similar to the
basic memory transactions discussed in the Basic PCI Master Read and Write Transactions section.
By definition, read and write transactions to I/O space are executed using 32-bit PCI transactions only. Driving all
32 bits of the address and byte enables (cben[3:0]) is required.
Advanced Master Transactions
Most PCI applications require more than basic read and write transactions. For these applications, the PCI IP core
offers advanced features to handle the more difficult aspects of the PCI bus. The advanced features are used to
provide the PCI application with more flexibility and improve the overall PCI system performance.
Wait States
Care must be taken when processing wait states to be compliant with the PCI Local Bus Specification, Revision
3.0. Once a PCI master or a PCI target signals that it is ready to send or receive data, it must complete the current
PCI data phase. For example, if the PCI IP core, as a target, is ready to write data and the PCI master inserts wait
states, the PCI IP core must wait to write the data until the master is ready again. Additionally, if the PCI IP core
asserts trdyn for a data phase, it cannot insert any wait states until the next data phase. Coincident master and
target wait state insertion is also a possibility. Refer to the PCI Specification for more information regarding coinci-
dent wait state insertion.
Two types of wait states occur on the PCI bus: master wait state insertion and target wait state insertion. When the
PCI master inserts wait states, the PCI IP core must hold off data until the PCI master is ready to complete the data
phase. The PCI IP core inserts the second type of wait states. The back-end application controls the PCI IP core’s
wait state insertion via the Local Master Interface.
Figure 2-13
and
Table 2-17
illustrate master-inserted and target-inserted wait states for read transactions. The fig-
ure illustrates the correlation between the PCI Interface and the Local Master Interface. The table gives a clock-by-
clock description of each event in the figure.
IPUG18_09.2, November 2010
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PCI IP Core User’s Guide