PCI-MT32-O4-N2 Lattice, PCI-MT32-O4-N2 Datasheet - Page 14

• Manufacturer Part Number: PCI-MT32-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-2. Signal Types
PCI Interface Signals
The PCI Interface signals correspond to the PCI bus specification.
the PCI IP core. These are the signals required by the PCI IP core to handle PCI bus side transactions.
describes each signal.
In addition to the signals required by the PCI IP core, there are some signals on the PCI Bus, referred to as “Addi-
tional Signals” in the PCI specifications, which must be handled appropriately to insure proper PCI IP core func-
tions in a system. Refer to the relevant PCI specifications for a description of those Additional Signals (which are
beyond the scope of this document). Examples of this type of signal are M66EN and PRSNT[1:0].
Table 2-3. PCI IP Core Signals
PCI System
clk
rstn
PCI Address and Data
ad[31:0]
cben[3:0
]
par
PCI Interface Control
framen
irdyn
trdyn
stopn
idsel
devseln
Name
Signal Type
s/t/s
s/t/s
s/t/s
s/t/s
s/t/s
I/O
s/t/s
t/s
t/s
t/s
in
in
in
out
o/d
t/s
in
Polarity
low
low
low
low
low
low
—
—
—
—
—
Input is a standard input only signal.
Output is a standard output only signal.
Tri-state is a bidirectional, tri-state input/output pin.
Sustained Tri-State is an active low tri-state signal owned and driven by one agent at a
time.
Open Drain allows multiple devices to share as a wire-OR. A pull-up is required to sustain
the inactive state until another agent drives it and must be provided by the central resource.
The PCI system clock provides timing for all transactions. The clock frequency operates up to
66MHz. This clock is also used to provide timing to the Local Interface.
The asynchronous PCI system reset is used to set the PCI device to a starting known and sta-
ble state.
The multiplexed address and data bus.
Multiplexed command and byte enable signals.
The par signal generates even parity for ad[31:0] and cben[3:0] signals
The framen signal is driven by the current master and used to indicate the start of cycle and
the duration of the cycle.
The initiator ready signal indicates that the current master is ready for the data phase.
The target ready signal indicates that the current target is ready for the data phase.
The PCI IP core, as a target, drives this signal low requesting to stop the current transaction.
The initialization device select is used to select a target for configuration reads and writes.
Device select is actively driven by the PCI IP core to indicate that it is the target of the bus
transaction.
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Description
Description
Table 2-3
shows the input and output signals for
Functional Description
PCI IP Core User’s Guide
Table 2-3