PCI-MT32-O4-N2 Lattice, PCI-MT32-O4-N2 Datasheet - Page 78

• Manufacturer Part Number: PCI-MT32-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-27. Fast Back-to-Back Transaction
CLK
1
2
3
4
5
6
7
8
PCI Data
Address
Phase
Wait
Wait
Idle
Idle
Idle
Idle
Idle
The local master asserts lm_req64n to request for 64-bit data transaction. It also issues the PCI
starting address, the bus command and the burst length on l_ad_in, lm_cben_in and
lm_burst_length respectively during the same clock cycle.
The Core’s Local Master Interface detects the asserted lm_req64n and asserts reqn to request
the use of PCI bus.
gntn is asserted to grant the Core access to the PCI bus. Core is now PCI master
Since gntn is asserted and the current bus is idle, the Core is going to start the bus transactions.
The Core asserts lm_gntn to inform the local master that the bus request is granted.
If both lm_req64n and lm_gntn were asserted on the previous cycle, lm_status[3:0] is
changed to ‘Address Loading’ to indicate the starting address, the bus command and the burst
length are being latched.
The local master keeps lm_req64n because it wants to request another PCI bus transaction for
fast back-to-back transaction.
The Core asserts framen and req64n to initiate the 64-bit write transaction when gntn was
asserted and lm_status[3:0] was ‘Address Loading’ on the previous cycle. It also drives the
PCI starting address on ad[31:0] and the PCI command on cben[3:0]. On the same cycle, it
outputs lm_status[3:0] as ‘Bus Transaction’ to indicate the beginning of the address/data
phases.
lm_burst_cnt gets the value of the burst length.
Because lm_rdyn was asserted on the previous cycle and the next cycle is the first data phase,
the local master provides Data 1 and Data 2 on l_ad_in[63:0] and the byte enables on
lm_cben_in[7:0]. And the Core asserts lm_ldata_xfern and lm_hdata_xfern to the local
master to signify these data and byte enables are being read and will be transferred to the PCI
bus.
Asserting lm_rdyn means the local master is ready to write data. If it is not, it keeps lm_rdyn de-
asserted until it is ready.
The Core keeps reqn when framen and lm_req64n were asserted to indicate fast back-to-back
transaction.
If the target completes the fast decode and is ready to receive 64-bit data, it asserts devseln,
ack64n and trdyn.
With lm_ldata_xfern and lm_hdata_xfern asserted on the previous cycle that was the
address phase, the local master should increment the address counter while the Core transfers
Data 1 and Data 2 and their byte enables to ad[63:0] and cben[7:0].
With lm_rdyn asserted on the previous cycle, the local master provides Data 3 and Data 4 on
l_ad_in[63:0] and the byte enables on lm_cben_in[7:0].
Because this is the first write data phase and devseln is just asserted, the Core keeps framen
asserted and irdyn de-asserted to judge 64-bit or 32-bit transaction. It also de-asserts
lm_ldata_xfern and lm_hdata_xfern to the local master to signify Data 3 and Data 4 on
l_ad_in[63:0] are not read.
If the local master is ready to provide the next QWORD, it keeps lm_rdyn asserted.
Since irdyn is not asserted, the first data phase is not completed.
Since lm_ldata_xfern and lm_hdata_xfern were not asserted on the previous cycle, the
local master keeps Data 3 and Data 4 on l_ad_in[63:0] and the byte enables on
lm_cben_in[7:0].
Because the Core needs one more cycle to decide 64-bit or 32-bit transaction, it keeps framen
asserted and irdyn de-asserted. It also keeps lm_ldata_xfern and lm_hdata_xfern de-
asserted to the local master to signify Data 3 and Data 4 on l_ad_in[63:0] are not read.
The Core asserts lm_64bit_transn to indicate the current data transaction is 64-bit wide. It de-
asserts lm_gntn to follow gntn.
If the local master is ready to provide the next QWORD, it keeps lm_rdyn asserted.
Since irdyn is not asserted, the first data phase is not completed.
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Description
Functional Description
PCI IP Core User’s Guide