PCI-MT32-O4-N2 Lattice, PCI-MT32-O4-N2 Datasheet - Page 27

• Manufacturer Part Number: PCI-MT32-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
Table 2-10. Customer Specific Parameters (Continued)
IPUG18_09.2, November 2010
rev_id_p
cls_code_p
dev_tim_p
cap_list_ena_p
cap_ptr_p
cis_ptr_p
fast_b2b_cap_p
irq_ack_ena_p
int_pin_p
hdw_lat_tmr_p
hdw_lat_tmr_
ena_p
min_gnt_p
max_lat_p
Configuration
Port Inputs
Space
REVISION_ID_g
CLASS_CODE_g
DEVSEL_TIMING_g
CAPABILITIES_LIST_
ENA_g
CAPABILITIES_POINTER_g
CIS_POINTER_g
FAST_B2B_CAP_g
IRQ_ACK_ENA_g
INTERRUPT_PIN_g
HARDWIRE_LATENCY_
TIMER_g
HARDWIRE_LATENCY_
TIMER_ENA_g
MIN_GNT_g
MAX_LAT_g
Corresponding Parameter
Name in PCI_params.v
Enabled/Disabled
0 - 0xFFFFFFFF 0x00000000
0 - 0xFFFFFF
0x00 - 0x01
0x0 - 0xFF
00 - 2’b10
Enabled/
Disabled
Enabled/
Disabled
Enabled/
Disabled
0 - 0xFF
0 - 0xFF
0 - 0xFF
0 - 0x10
Range
27
0x000000
Disabled
Enabled
Enabled
Enabled
Default
2’b10
0x00
0x40
0x01
0x00
0x00
0x00
Value for Revision ID field in the Configura-
tion Space. This value correlates to the lower
8 bits of register 08h.
Value for Class Code field in the Configura-
tion Space. This is the value of the upper 24
bits of register 08h. Class Code is further
subdivided into Base Class, Sub Class, and
Interface values. Refer to the PCI local bus
specification for valid Class codes.
Controls bits 9 and 10 in the status register,
located at the upper 16 bits of address 04h.
This parameter is used to define the decode
speed of the PCI IP core.
00 - Fast (not supported)
01 - Medium (not supported)
10 - Slow
11 - Reserved
Enable for the Capabilities Pointer. It is used
to set the enable bit for the Capabilities List in
the PCI Status register. This bit is used to
indicate if the value of the Capabilities Pointer
at location 34h is valid. This is bit 4 in the sta-
tus register.
Value for Capabilities Pointer field in the Con-
figuration Space. This is an 8-bit value
located at 34h.
Value for the Cardbus CIS Pointer field in the
Configuration Space. This is a 32-bit value
located at 28h in the Configuration Space
Settings for the CIS Pointer are beyond the
scope of this document. For more information
on setting this register, refer to the CardBus
specification.
Value for the Status field bit to enable fast
back-to-back transfers. This is bit 7 of the sta-
tus register.
Enable response to the Interrupt Acknowl-
edge PCI command.
Value for Interrupt Pin field in the Configura-
tion Space. If set, it allows the local interrupt
signal l_interruptn to appear on the PCI
Interrupt intan. If the local interrupt is not
used, it must be tied high.
Value for read-only latency timer register
Enable read only latency timer register.
Value for MIN_GRAND field in the configura-
tion space.
Value for MAX_LATENCY field in the configu-
ration space.
Functional Description
Description
PCI IP Core User’s Guide