PCI-MT32-O4-N2 Lattice, PCI-MT32-O4-N2 Datasheet - Page 88

• Manufacturer Part Number: PCI-MT32-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-31. 64-bit Target Single Read Transaction with a 64-bit Local Interface
CLK
10
1
2
3
4
5
6
9
Turn around
Turn around
PCI Data
Address
Phase
Data 1
Wait
Wait
Wait
Idle
The master asserts framen, req64n and drives ad[31:0] and cben[3:0].
The master tri-states the ad[63:0] lines and drives the first byte enables (Byte Enable 1 and 2).
If the master is ready to receive data, it asserts irdyn.
The Core starts to decode the address and command. The Core drives the lt_address_out to
the back-end. The lt_64bit_transn signal is driven low to signal the back-end that a 64-bit
transaction has been requested.
If an address match is present, the Core drives the bar_hit signals to the back-end. The back-
end can use the bar_hit as a chip select.
If the DEVSEL_TIMING is set to slow, the Core asserts devseln one clock after bar_hit. The
ack64n signal is also asserted to acknowledge the 64-bit request. If the back-end is ready to put
data out on the next cycle, it can assert lt_rdyn.
The local target asserts lt_hdata_xfern and lt_ldata_xfern since lt_rdyn was asserted
the previous cycle. The back-end drives the first QWORD (Data 1) on l_ad_in[63:0].
With lt_rdyn asserted during the previous two cycles, the burst cycle starts the Core asserts
trdyn and puts Data 1 on ad[31:0].
With lt_rdyn asserted previous two cycles, the burst cycle starts. The Core asserts trdyn and
puts Data 1 on ad[63:0].
If both irdyn and lt_rdyn are asserted on the previous cycle, the Core keeps
lt_hdata_xfern and lt_ldata_xfern asserted to the back-end. The back-end can incre-
ment the address counter and put the next QWORD (Don’t care) on l_ad_in[63:0].
The master relinquishes control of framen, ack64n and cben[7:0]. It de-asserts irdyn if both
trdyn and irdyn were asserted last cycle.
The Core relinquishes control of ad[63:0]. It de-asserts both devseln and trdyn if both
trdyn and irdyn were asserted during the last cycle. The Core also clears bar_hit to signal to
the back-end that the transaction is complete. The Core de-asserts lt_hdata_xfern and
lt_ldata_xfern.
88
Description
Functional Description
PCI IP Core User’s Guide