PCI-MT32-O4-N2 Lattice, PCI-MT32-O4-N2 Datasheet - Page 142

• Manufacturer Part Number: PCI-MT32-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
Parameter Settings
Base Address Registers
Number of BARs
The number of Base Address Registers configured by the user.
BAR0 - BAR5
The Base Address value used to map memory or I/O address space.
BAR Configuration Options
Figure 3-6
shows the BAR Configuration dialog box, which is displayed when the Configure button is pressed in
the BARs tab.
Figure 3-6. BAR Configuration Options
BAR Width
The width of the Base Address Register. When using 64-bit width, the current BAR and next BAR will combine as
the 64-bit Base Address.
BAR Type
Used to map memory or I/O space.
Address Space Size
The parameter is the size of the address range mapped to memory or I/O space.
Prefetching Enable
This option determines if the memory mapped by this BAR support prefetching operation.
IPUG18_09.2, November 2010
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PCI IP Core User’s Guide