PCI-MT32-O4-N2 Lattice, PCI-MT32-O4-N2 Datasheet - Page 37

• Manufacturer Part Number: PCI-MT32-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-13. 64-bit Master Single Read Transaction with a 64-bit Local Interface
CLK
10
11
1
2
3
4
5
6
7
8
9
Data 1 and 2
Turn around
Turn around
Address
Phase
Wait
Idle
Idle
Idle
Idle
Idle
Idle
The local master asserts lm_req64n for the 64-bit data transaction request. It also puts the PCI
starting address, the bus command, and the burst length during the same clock cycle on
l_ad_in, lm_cben_in, and lm_burst_length, respectively.
The Core's Local Master Interface detects the asserted lm_req64n and asserts reqn to request
the use of PCI bus.
gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master.
Since gntn is asserted and the current bus is idle, the Core is going to start the bus transactions.
The master asserts lm_gntn to inform the local master that the bus request is granted.
If both lm_req64n and lm_gntn are asserted on the previous cycle, lm_status[3:0] is
changed to ‘Address Loading’ to indicate the starting address, the bus command and the burst
length are latched.
The local master de-asserts lm_req64n when the previous lm_status[3:0] was ‘Address
Loading’ and if it doesn’t want to request another PCI bus transaction.
The Core asserts framen and req64n to initiate the 64-bit read transaction when gntn was still
asserted and lm_status[3:0] was ‘Address Loading’ on the previous cycle. It also drives the
PCI starting address on ad[31:0] and the PCI command on cben[3:0]. On the same cycle, it
outputs lm_status[3:0] as ‘Bus Transaction’ to indicate the beginning of the address/data
phases.
lm_burst_cnt gets the value of the burst length.
Because lm_rdyn was asserted on the previous cycle and the next cycle is the first data phase,
the local master provides the byte enables on lm_cben_in[7:0]. Asserting lm_rdyn also
means the local master is ready to read data for the single data transaction. If it is not ready to
read data, it keeps lm_rdyn de-asserted until it is ready.
The Core de-asserts reqn when framen was asserted but lm_req64n was de-asserted on the
previous cycle. The target asserts devseln and ack64n to indicate it acknowledges the 64-bit
transaction. The Core tri-states the ad[63:0] lines and drives the byte enables (Byte Enable 1
and 2).
The Core asserts lm_64bit_transn to indicate the current data transaction is 64 bits wide. It
de-asserts lm_gntn to follow gntn.
The target asserts trdyn and puts Data 1 and 2 on ad[63:0].
If the local master is ready to read the 64-bit word (QWORD), it keeps lm_rdyn asserted.
Since lm_rdyn was asserted on the previous cycle, it asserts irdyn to indicate it is ready to
read data. Since both irdyn and trdyn are asserted, the first data phase is completed on this
cycle.
Since the previous data phase was completed, the Core transfers Data 1 and 2 on
l_data_out[63:0] and decreases the lm_burst_cnt to zero.
The Core relinquishes control of framen, req64n and cben. It de-asserts irdyn and changes
lm_status[3:0] into ‘Bus Termination’ with lm_termination as ‘Normal Termination’
because both trdyn and irdyn were asserted last cycle.
The target relinquishes control of ad[63:0]. It de-asserts devseln, ack64n and trdyn.
If both trdyn and lm_rdyn were asserted on the previous cycle, the Core asserts
lm_ldata_xfern and lm_hdata_xfern to the local master to signify Data 1 and 2 are avail-
able on l_data_out[63:0]. With lm_ldata_xfern and lm_hdata_xfern asserted, the
local master safely reads Data 1 and 2.
The Core relinquishes control of irdyn and de-asserts lm_ldata_xfern and
lm_hdata_xfern, and the local master de-asserts lm_rdyn since all of the burst data have
been read.
37
Description
Functional Description
PCI IP Core User’s Guide