LFE3-150EA-6LFN672C Lattice, LFE3-150EA-6LFN672C Datasheet - Page 138

• Manufacturer Part Number: LFE3-150EA-6LFN672C
• Description: FPGA - Field Programmable Gate Array 149K LUTs 380 I/O 1.2V -6 SPEED
• Manufacturer: Lattice

Specifications of LFE3-150EA-6LFN672C

• Rohs: yes
• Factory Pack Quantity: 40

September 2009
November 2009
August 2009
May 2009
July 2009
(cont.)
Date
Version
(cont.)
01.1
01.2
01.3
01.4
01.5
Pinout Information
Pinout Information
DC and Switching
DC and Switching
DC and Switching
DC and Switching
Characteristics
Characterisitcs
Characterisitcs
Characterisitcs
Architecture
Architecture
Architecture
Introduction
Section
Multiple
(cont.)
Updated timing information
Updated SERDES minimum frequency.
Added data to the following tables: External Switching Characteristics,
Internal Switching Characteristics, Family Timing Adders, Maximum I/O
Buffer Speed, DLL Timing, High Speed Data Transmitter, Channel Out-
put Jitter, Typical Building Block Function Performance, Register-to-
Register Performance, and Power Supply Requirements.
Updated Serial Input Data Specifications table.
Updated Transmit table, Serial Rapid I/O Type 2 Electrical and Timing
Characteristics section.
Updated Signal Description tables.
Updated Pin Information Summary tables and added footnote 1.
Changed references of “multi-boot” to “dual-boot” throughout the data
sheet.
Updated On-Chip Programmable Termination bullets.
Updated On-Chip Termination Options for Input Modes table.
Updated On-Chip Termination figure.
Changed min/max data for FREF_PPM and added footnote 4 in
SERDES External Reference Clock Specification table.
Updated SERDES minimum frequency.
Corrected MCLK to be I/O and CCLK to be I in Signal Descriptions table
Corrected truncated numbers for V
Operating Conditions table.
Corrected link in sysMEM Memory Block section.
Updated information for On-Chip Programmable Termination and modi-
fied corresponding figure.
Added footnote 2 to On-Chip Programmable Termination Options for
Input Modes table.
Corrected Per Quadrant Primary Clock Selection figure.
Modified -8 Timing data for 1024x18 True-Dual Port RAM (Read-Before-
Write, EBR Output Registers)
Added ESD Performance table.
LatticeECP3 External Switching Characteristics table - updated data for
t
LatticeECP3 Internal Switching Characteristics table - updated data for
t
sysCLOCK PLL Timing table - updated data for f
External Reference Clock Specification (refclkp/refclkn) table - updated
data for V
LatticeECP3 sysCONFIG Port Timing Specifications table - updated
data for t
Added TRLVDS DC Specification table and diagram.
Updated Mini LVDS table.
Updated Embedded SERDES features.
Added SONET/SDH to Embedded SERDES protocols.
Updated Figure 2-4, General Purpose PLL Diagram.
Updated SONET/SDH to SERDES and PCS protocols.
DIBGDDR
COO_PIO
7-2
, t
MWC
and added footnote #4.
REF-IN-SE
W_PRI
.
, t
W_EDGE
and V
REF-IN-DIFF
Change Summary
and t
LatticeECP3 Family Data Sheet
SKEW_EDGE_DQS
CCIB
.
and V
CCOB
Revision History
.
OUT
in Recommended
.