LFE3-150EA-6LFN672C Lattice, LFE3-150EA-6LFN672C Datasheet - Page 33

• Manufacturer Part Number: LFE3-150EA-6LFN672C
• Description: FPGA - Field Programmable Gate Array 149K LUTs 380 I/O 1.2V -6 SPEED
• Manufacturer: Lattice

Specifications of LFE3-150EA-6LFN672C

• Rohs: yes
• Factory Pack Quantity: 40

ALU Flags
The sysDSP slice provides a number of flags from the ALU including:
Clock, Clock Enable and Reset Resources
Global Clock, Clock Enable and Reset signals from routing are available to every sysDSP slice. From four clock
sources (CLK0, CLK1, CLK2, and CLK3) one clock is selected for each input register, pipeline register and output
register. Similarly Clock Enable (CE) and Reset (RST) are selected at each input register, pipeline register and out-
put register.
Resources Available in the LatticeECP3 Family
Table 2-9 shows the maximum number of multipliers for each member of the LatticeECP3 family. Table 2-10 shows
the maximum available EBR RAM Blocks in each LatticeECP3 device. EBR blocks, together with Distributed RAM
can be used to store variables locally for fast DSP operations.
Table 2-9. Maximum Number of DSP Slices in the LatticeECP3 Family
Table 2-10. Embedded SRAM in the LatticeECP3 Family
• Equal to zero (EQZ)
• Equal to zero with mask (EQZM)
• Equal to one with mask (EQOM)
• Equal to pattern with mask (EQPAT)
• Equal to bit inverted pattern with mask (EQPATB)
• Accumulator Overflow (OVER)
• Accumulator Underflow (UNDER)
• Either over or under flow supporting LatticeECP2 legacy designs (OVERUNDER)
ECP3-150
ECP3-17
ECP3-35
ECP3-70
ECP3-95
Device
DSP Slices
ECP3-150
ECP3-17
ECP3-35
ECP3-70
ECP3-95
Device
160
12
32
64
64
EBR SRAM Block
9x9 Multiplier
2-30
128
256
256
640
240
240
372
48
38
72
Total EBR SRAM
18x18 Multiplier
LatticeECP3 Family Data Sheet
(Kbits)
1327
4420
4420
6850
128
128
320
700
24
64
36x36 Multiplier
Architecture
16
32
32
80
6