LFE3-150EA-6LFN672C Lattice, LFE3-150EA-6LFN672C Datasheet - Page 67

• Manufacturer Part Number: LFE3-150EA-6LFN672C
• Description: FPGA - Field Programmable Gate Array 149K LUTs 380 I/O 1.2V -6 SPEED
• Manufacturer: Lattice

Specifications of LFE3-150EA-6LFN672C

• Rohs: yes
• Factory Pack Quantity: 40

Typical Building Block Function Performance
Pin-to-Pin Performance (LVCMOS25 12mA Drive)
Register-to-Register Performance
Basic Functions
16-bit Decoder
32-bit Decoder
64-bit Decoder
4:1 MUX
8:1 MUX
16:1 MUX
32:1 MUX
1. These functions were generated using the ispLEVER design tool. Exact performance may vary with device and tool version. The tool uses
2. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Diamond or ispLEVER soft-
Basic Functions
16-bit Decoder
32-bit Decoder
64-bit Decoder
4:1 MUX
8:1 MUX
16:1 MUX
32:1 MUX
8-bit adder
16-bit adder
64-bit adder
16-bit counter
32-bit counter
64-bit counter
64-bit accumulator
Embedded Memory Functions
512x36 Single Port RAM, EBR Output Registers
1024x18 True-Dual Port RAM (Write Through or Normal, EBR Output Registers)
1024x18 True-Dual Port RAM (Read-Before-Write, EBR Output Registers
1024x18 True-Dual Port RAM (Write Through or Normal, PLC Output Registers)
Distributed Memory Functions
16x4 Pseudo-Dual Port RAM (One PFU)
32x4 Pseudo-Dual Port RAM
64x8 Pseudo-Dual Port RAM
DSP Function
18x18 Multiplier (All Registers)
9x9 Multiplier (All Registers)
36x36 Multiply (All Registers)
internal parameters that have been characterized but are not tested on every device.
ware.
Function
Function
1, 2, 3
3-14
1, 2, 3
DC and Switching Characteristics
LatticeECP3 Family Data Sheet
-9 Timing
-9 Timing
500
500
500
500
500
500
487
500
500
336
500
500
350
326
358
358
136
260
500
500
442
420
420
281
3.8
3.8
5.4
4.0
4.2
4.5
4.7
Units
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns