LFE3-150EA-6LFN672C Lattice, LFE3-150EA-6LFN672C Datasheet - Page 44

• Manufacturer Part Number: LFE3-150EA-6LFN672C
• Description: FPGA - Field Programmable Gate Array 149K LUTs 380 I/O 1.2V -6 SPEED
• Manufacturer: Lattice

Specifications of LFE3-150EA-6LFN672C

• Rohs: yes
• Factory Pack Quantity: 40

Figure 2-38. LatticeECP3 Banks
LatticeECP3 devices contain two types of sysI/O buffer pairs.
1. Top (Bank 0 and Bank 1) and Bottom sysIO Buffer Pairs (Single-Ended Outputs Only)
The sysI/O buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of
single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be con-
figured as a differential input. Only the top edge buffers have a programmable PCI clamp.

The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer. 

The top and bottom sides are ideal for general purpose I/O, PCI, and inputs for LVDS (LVDS outputs are only
allowed on the left and right sides). The top side can be used for the DDR3 ADDR/CMD signals. 

The I/O pins located on the top and bottom sides of the device are fully hot socketable.
V REF1(7)
V REF2(7)
V
V REF1(6)
V REF2(6)
V CCIO6
CCIO7
GND
GND
Bank 0
BOTTOM
SERDES
TOP
Quads
2-41
Bank 1
LatticeECP3 Family Data Sheet
V REF1(2)
V REF2(2)
V CCIO2
GND
V REF1(3)
V REF2(3)
V CCIO3
GND
Architecture