LFE3-150EA-6LFN672C Lattice, LFE3-150EA-6LFN672C Datasheet - Page 71

• Manufacturer Part Number: LFE3-150EA-6LFN672C
• Description: FPGA - Field Programmable Gate Array 149K LUTs 380 I/O 1.2V -6 SPEED
• Manufacturer: Lattice

Specifications of LFE3-150EA-6LFN672C

• Rohs: yes
• Factory Pack Quantity: 40

LatticeECP3 External Switching Characteristics (Continued)
t
t
t
t
t
t
t
t
t
t
t
t
t
Generic DDR
Generic DDRX1 Inputs with Clock and Data (>10 Bits Wide) Centered at Pin (GDDRX1_RX.SCLK.Centered) Using PCLK Pin for Clock
Input
t
t
f
Generic DDRX1 Inputs with Clock and Data (>10 Bits Wide) Aligned at Pin (GDDRX1_RX.SCLK.PLL.Aligned) Using PLLCLKIN Pin for
Clock Input
Data Left, Right, and Top Sides and Clock Left and Right Sides
t
t
f
Generic DDRX1 Inputs with Clock and Data (>10 Bits Wide) Aligned at Pin (GDDRX1_RX.SCLK.Aligned) Using DLL - CLKIN Pin for
Clock Input
Data Left, Right and Top Sides and Clock Left and Right Sides
t
t
f
Generic DDRX1 Inputs with Clock and Data (<10 Bits Wide) Centered at Pin (GDDRX1_RX.DQS.Centered) Using DQS Pin for Clock
Input
t
t
f
Generic DDRX1 Inputs with Clock and Data (<10bits wide) Aligned at Pin (GDDRX1_RX.DQS.Aligned) Using DQS Pin for Clock Input
Data and Clock Left and Right Sides
t
HPLL
SU_DELPLL
H_DELPLL
COPLL
SUPLL
HPLL
SU_DELPLL
H_DELPLL
COPLL
SUPLL
HPLL
SU_DELPLL
H_DELPLL
SUGDDR
HOGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
SUGDDR
HOGDDR
MAX_GDDR
DVACLKGDDR
Parameter
12
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO Input
Register with Data Input Delay
Clock to Data Hold - PIO Input
Register with Input Data Delay
Clock to Output - PIO Output
Register
Clock to Data Setup - PIO Input
Register
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO Input
Register with Data Input Delay
Clock to Data Hold - PIO Input
Register with Input Data Delay
Clock to Output - PIO Output
Register
Clock to Data Setup - PIO Input
Register
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO Input
Register with Data Input Delay
Clock to Data Hold - PIO Input
Register with Input Data Delay
Data Setup Before CLK
Data Hold After CLK
DDRX1 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX1 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX1 Clock Frequency
Data Setup After CLK
Data Hold After CLK
DDRX1 Clock Frequency
Data Setup Before CLK
Description
Over Recommended Commercial Operating Conditions
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
All ECP3EA Devices
All ECP3EA Devices
All ECP3EA Devices
All ECP3EA Devices
All ECP3EA Devices 0.775
All ECP3EA Devices
All ECP3EA Devices
All ECP3EA Devices 0.775
All ECP3EA Devices
All ECP3EA Devices
All ECP3EA Devices
All ECP3EA Devices
All ECP3EA Devices
Device
3-18
Min. Max. Min. Max. Min. Max. Min. Max.
480
480
535
535
0.7
1.6
0.0
0.6
0.3
1.6
0.0
—
—
—
—
—
—
—
—
—
—
—
—
—
-9
0.225
0.225
0.225
250
250
250
250
DC and Switching Characteristics
3.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LatticeECP3 Family Data Sheet
0.775
0.775
480
480
535
535
0.7
1.6
0.0
0.6
0.3
1.6
0.0
0.6
0.3
1.6
0.0
—
—
—
—
—
—
—
—
—
-8
0.225
0.225
0.225
250
250
250
250
3.2
3.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.775
0.775
480
480
535
535
0.7
1.8
0.0
0.7
0.3
1.7
0.0
0.7
0.3
1.7
0.0
—
—
—
—
—
—
—
—
—
1, 2
-7
0.225
0.225
0.225
250
250
250
250
3.4
3.3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.775
0.775
480
480
535
535
0.8
2.0
0.0
0.8
0.4
1.8
0.0
0.8
0.4
1.8
0.0
—
—
—
—
—
—
—
—
—
-6
0.225
0.225
0.225
250
250
250
250
3.6
3.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
UI
UI
UI
UI
ps
ps
UI