LFE3-150EA-6LFN672C Lattice, LFE3-150EA-6LFN672C Datasheet - Page 87

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LFE3-150EA-6LFN672C

Manufacturer Part Number
LFE3-150EA-6LFN672C
Description
FPGA - Field Programmable Gate Array 149K LUTs 380 I/O 1.2V -6 SPEED
Manufacturer
Lattice
Datasheet

Specifications of LFE3-150EA-6LFN672C

Rohs
yes
Factory Pack Quantity
40

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFE3-150EA-6LFN672C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
sysCLOCK PLL Timing
Parameter
f
f
f
f
f
f
AC Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock with no additional I/O toggling.
2. Output clock is valid after t
3. Period jitter and cycle-to-cycle jitter numbers are guaranteed for
4. When using internal feedback, maximum can be up to 500 MHz.
IN
OUT
OUT1
OUT2
VCO
PFD
PA
DT
CPA
OPW
OPJIT
SK
LOCK
UNLOCK
HI
LO
IPJIT
RST
tain conditions. Please contact the factory for
3
2
1
Input clock frequency (CLKI,
CLKFB)
Output clock frequency (CLKOP,
CLKOS)
K-Divider output frequency
K2-Divider output frequency
PLL VCO frequency
Phase detector input frequency
Programmable delay unit
Output clock duty cycle
(CLKOS, at 50% setting)
Coarse phase shift error
(CLKOS, at all settings)
Output clock pulse width high or
low
(CLKOS)
Output clock period jitter
Input clock to output clock skew
when N/M = integer
Lock time
Reset to PLL unlock time to
ensure fast reset
Input clock high time
Input clock low time
Input clock period jitter
Reset signal pulse width high,
RSTK
Reset signal pulse width high,
RST
Descriptions
LOCK
for PLL reset and dynamic delay adjustment.
Over Recommended Operating Conditions
f
PFD
CLKOK
CLKOK2
f
f
f
420MHz > f
f
2 to 25 MHz
25 to 500 MHz
90% to 90%
10% to 10%
OUT
OUT
OUT
OUT
< 4MHz.
250 MHz
> 250MHz
 420MHz
< 100MHz
Conditions
OUT
f
PFD
3-34
 100MHz
> 4MHz. For
Edge clock
Primary clock
Edge clock
Primary clock
Edge clock
Primary clock
Edge clock
Primary clock
Primary clock
f
PFD
DC and Switching Characteristics
Clock
< 4MHz, the jitter numbers may not be met in cer-
LatticeECP3 Family Data Sheet
4
4
4
0.03125
0.667
Min.
500
1.8
0.5
500
0.5
65
45
45
30
10
-5
2
2
4
4
2
2
Typ.
130
50
50
50
0
0.025
Max.
1000
500
420
500
420
250
166
500
420
260
200
250
500
200
400
+5
55
55
70
50
50
period
Units
UIPP
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
% of
ps
ns
ps
ps
ps
us
us
ns
ns
ns
ps
ns
ns
%
%
%

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