LFE3-150EA-6LFN672C Lattice, LFE3-150EA-6LFN672C Datasheet - Page 55

• Manufacturer Part Number: LFE3-150EA-6LFN672C
• Description: FPGA - Field Programmable Gate Array 149K LUTs 380 I/O 1.2V -6 SPEED
• Manufacturer: Lattice

Specifications of LFE3-150EA-6LFN672C

• Rohs: yes
• Factory Pack Quantity: 40

Hot Socketing Specifications
Hot Socketing Requirements
ESD Performance
Please refer to the
ESD performance.
IDK_HS
IDK
1. V
2. I
3. LVCMOS and LVTTL only.
4. Applicable to general purpose I/O pins located on the top and bottom sides of the device.
5. Applicable to general purpose I/O pins located on the left and right sides of the device.
Input current per SERDES I/O pin when device is powered down and inputs
driven.
1. Assumes the device is powered down, all supplies grounded, both P and N inputs driven by CML driver with maximum allowed VCCOB
2. Each P and N input must have less than the specified maximum input current. For a 16-channel device, the total input current would be
Symbol
(1.575V), 8b10b data, internal AC coupling.
8mA*16 channels *2 input pins per channel = 256mA
DK
5
CC
is additive to I
, V
4
CCAUX
Input or I/O Leakage Current
Input or I/O Leakage Current
and V
PU
CCIO
, I
LatticeECP3 Product Family Qualification Summary
PW
Parameter
should rise/fall monotonically.
or I
BH
.
Description
0 V
0  V
V
CCIO
1, 2
1, 2, 3
IN
IN
 V
 V
< V
Condition
IN
IH
CCIO
 V
(Max.)
CCIO
3-2
+ 0.5V
DC and Switching Characteristics
Min.
Min.
for complete qualification data, including
—
—
—
—
LatticeECP3 Family Data Sheet
Typ.
Typ.
18
—
—
—
Max.
Max.
+/-1
+/-1
—
8
Units
Units
mA
mA
mA
mA