LFE3-150EA-6LFN672C Lattice, LFE3-150EA-6LFN672C Datasheet - Page 25

• Manufacturer Part Number: LFE3-150EA-6LFN672C
• Description: FPGA - Field Programmable Gate Array 149K LUTs 380 I/O 1.2V -6 SPEED
• Manufacturer: Lattice

Specifications of LFE3-150EA-6LFN672C

• Rohs: yes
• Factory Pack Quantity: 40

For most cases, as shown in Figure 2-24, the LatticeECP3 DSP slice is backwards-compatible with the
LatticeECP2™ sysDSP block, such that, legacy applications can be targeted to the LatticeECP3 sysDSP slice. The
functionality of one LatticeECP2 sysDSP Block can be mapped into two adjacent LatticeECP3 sysDSP slices, as
shown in Figure 2-25.
Figure 2-24. Simplified sysDSP Slice Block Diagram
• RTL Synthesis friendly synchronous reset on all registers, while still supporting asynchronous reset for legacy
• Dynamic MUX selection to allow Time Division Multiplexing (TDM) of resources for applications that require
– Flexible cascading across slices to get larger functions
users
processor-like flexibility that enables different functions for each clock cycle
Intermediate Pipeline
as, overflow, underflow and convergent rounding, etc.
Output Registers
ALU Op-Codes
Input Registers
Left-side DSP
Cascade from
from SRO of
Registers
Left DSP
9x9
OR
Mult18-0
MULTA
Accumulator/ALU (54)
PR
IR
IR
9x9
OR
9x9
OR
Slice 0
Mult18-1
MULTB
PR
IR
IR
9x9
OR
From FPGA Core
To FPGA Core
Carry
Reg.
Out
2-22
Casc
A0
9x9
OR
Mult18-0
MULTA
Accumulator/ALU (54)
PR
IR
IR
9x9
OR
LatticeECP3 Family Data Sheet
Slice 1
9x9
OR
Mult18-1
MULTB
PR
IR
IR
9x9
OR
Carry
Reg.
Casc
Out
A1
One of
these
Architecture
Cascade to
Right DSP