74VHC112M_Q Fairchild Semiconductor, 74VHC112M_Q Datasheet - Page 2

• Manufacturer Part Number: 74VHC112M_Q
• Description: Flip Flops Dual J-K Flip-Flops
• Manufacturer: Fairchild Semiconductor

Specifications of 74VHC112M_Q

• Number Of Circuits: 2
• Logic Family: 74VHC
• Logic Type: J-K Flip-Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Output Type: Differential
• Propagation Delay Time: 15 ns
• High Level Output Current: - 8 mA
• Low Level Output Current: 8 mA
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-16
• Minimum Operating Temperature: - 40 C
• Number Of Input Lines: 2
• Number Of Output Lines: 1
• Supply Voltage - Min: 2 V

©1995 Fairchild Semiconductor Corporation
74VHC112 Rev. 1.2
Connection Diagram
Pin Description
Logic Diagram
(One Half Shown)
J
CLK
CLR
PR
Q
1
1
, J
Pin Names
, Q
1
, PR
1
2
1
, CLK
, K
, CLR
2
, Q
1
2
, K
1
, Q
2
2
2
2
Data Inputs
Clock Pulse Inputs (Active Falling
Edge)
Direct Clear Inputs (Active LOW)
Direct Preset Inputs (Active LOW)
Outputs
Description
2
Truth Table
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
X = Immaterial
Q
Lower case letters indicate the state of the referenced
input or output one setup time prior to the HIGH-to-LOW
clock transition.
0
PR
H
H
H
H
H
(Q
L
L
= HIGH-to-LOW Clock Transition
0
) = Before HIGH-to-LOW Transition of Clock
CLR
H
H
H
H
H
L
L
Inputs
CP
X
X
X
J
X
X
X
h
h
l
l
K
X
X
X
h
h
l
l
Q
Q
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Q
H
H
H
Outputs
L
L
0
0
Q
Q
Q
H
H
H
L
L
0
0