ISL6146AFRZ-T7A Intersil, ISL6146AFRZ-T7A Datasheet - Page 18

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ISL6146AFRZ-T7A

Manufacturer Part Number
ISL6146AFRZ-T7A
Description
Hot Swap & Power Distribution LW VOLT ORING FET CONTRLR 3X3 8LD DFN
Manufacturer
Intersil
Datasheet

Specifications of ISL6146AFRZ-T7A

Product Category
Hot Swap & Power Distribution
Rohs
yes
Product
Controllers & Switches
Current Limit
6 A
Supply Voltage - Max
20 V
Supply Voltage - Min
1 V
Operating Temperature Range
- 40 C to + 125 C
Mounting Style
SMD/SMT
Package / Case
DFN-8
Input / Supply Voltage (max)
20 V
Input / Supply Voltage (min)
1 V
Number Of Channels
1
Supply Current
25 uA
Applications Information
Power-Up Considerations
BIAS AND V
Upon power-up when the V
supply, the BIAS voltage must be greater or equal to the V
voltage at all times.
When using a single supply for both the ISL6146 bias and the
OR-ing supply, the V
value resistor between the two pins to provide some isolation and
decoupling to support the chip bias even as the OR’d supply
experiences voltage droops and surges. Although not necessary
to do so, it is a best design practice for particularly noisy
environments.
FET TO IC LAYOUT RECOMMENDATIONS
Connections from the FET(s) to the ISL6146 VIN and VOUT pins
must be Kelvin in nature and as close to the FET drain and source
PCB pads as possible to eliminate any trace resistance errors
that can occur with high currents. This connection placement is
most critical to providing the most accurate voltage sensing
particularly when the back-to-back FET configuration is used.
Likewise, connections from OVP, UVLO and ADJ are also critical to
optimize accuracy.
ADJUSTING THE HS COMPARATOR REVERSE VOLTAGE
THRESHOLD
The ISL6146 allows adjustment of the HS Comparator reverse
voltage detection threshold (VR Vth), the difference in V
There are two valid ADJ pin configurations:
So, for a 100kΩ R
VOUT and for a 5kΩ R
below VOUT.
The recommended resistor range is 5kΩ to 100kΩ for this
voltage adjustment.
At power-up, the HS comparator threshold is default set to the
internal device error first, and then released to the user
programmed threshold after the related circuits are ready. It
takes ~20μs for the circuit to switch from the default setting to
the user programmed threshold after a POR startup.
The current out of the ADJ pin with a resistor to GND is equal to
0.4V/R
BACK-TO-BACK FET CONFIGURATION
When using the back-to-back FET configuration, the FET choice
must be such that the voltage across both FETs at full current
loading be less than the minimum forward voltage fault
threshold of 400mV to avoid unintended fault notification.
1. ADJ connected to VOUT: This makes the HS comparator
2. A single resistor is connected from ADJ pin to ground:
threshold equal to the intrinsic error in the HS comparator
input. This is the default condition and the most likely used
configuration.
Making the HS comparator threshold = V
EXT.
IN
CONSTRAINTS
EXT
IN
, HS Comparator threshold = 40mV below
EXT
and BIAS pins can be configured with a low
HS comparator threshold = ~ 800mV
IN
supply is separate from the BIAS
18
OUT
- 4k/R
OUT
ADJ
IN
.
ISL6146
- V
IN
.
In this configuration, it may be tempting to use the enable inputs
to force a path by switching between the two as opposed to
having both paths on, and having the higher voltage source
provide current. The problem with that is the timing of the FETs
on and off, so that excessive V
if the turn-off happens faster, or before the (or a slower) turn-on
momentarily leaves the load with an inadequate power
connection.
Typical Applications Circuits
There are four basic configurations that the ISL6146 can be
used in:
Each of these configurations can be tailored for the High Speed
Comparator (HS COMP) reverse threshold via the ADJ input being
connected either to VOUT or to GND via a resistor as previously
explained. Additionally, the voltage window is adjustable for both
a minimum and maximum operating voltage via the UVLO and
OVP inputs and a resistor divider also explained earlier. Also,
soft-start and turn-on and turn-off characteristics can be tailored
to suit.
The three evaluation platforms provided demonstrate the four
basic configurations and provide for the additional tailoring of
the various performance characteristics.
1. For voltages >3V where the BIAS and V
2. For a very low OR-ing voltage, <3V operation, BIAS >3V
3. For a voltage window compliant operation and,
4. For a signaled operation where the current path is controlled
by an input signal or minimum voltage condition.
VOLTAGE
VERY LOW
VERY LOW
VOLTAGE
VOLTAGE
DC - DC
DC - DC
BIAS
(1V-3V)
(1V-3V)
>3V
FIGURE 47. LOW VOLTAGE APPLICATION DIAGRAM
+
+
-
-
VIN
BIAS
EN
VIN
BIAS
EN
ISL6146A
ISL6146A
GATE
GATE
OUT
GND
GND
Q1
Q2
voltage droop is not introduced
VOUT
VOUT
ADJ
ADJ
FLT
FLT
IN
are common
April 26, 2013
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FN7667.4
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