PCF85102C-2T/03,11 NXP Semiconductors, PCF85102C-2T/03,11 Datasheet - Page 11

• Manufacturer Part Number: PCF85102C-2T/03,11
• Description: IC EEPROM 2KBIT 100KHZ 8SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCF85102C-2T/03,11

• Memory Size: 2K (256 x 8)
• Package / Case: 8-SOIC (3.9mm Width)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 100kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 6.0 V
• Operating Temperature: -40°C ~ 85°C
• Organization: 256 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.1 MHz
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935262037118; PCF85102C2D-T; PCF85102C2D-T

Philips Semiconductors
11. I
Table 8:
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to V
with an input voltage swing from V
[1]
9397 750 14216
Product data
Symbol
f
t
t
t
t
t
t
t
t
t
t
SCL
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
r
f
SU;STO
Fig 9. Timing requirements for the I
SCL
SDA
The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by
a transmitter.
P = STOP condition; S = START condition.
2
C-bus characteristics
I
P
2
C-bus characteristics
Parameter
clock frequency
bus free time between a STOP and
START condition
START condition hold time after
which first clock pulse is generated
LOW level clock period
HIGH level clock period
set-up time for START condition
data hold time
data set-up time
SDA and SCL rise time
SDA and SCL fall time
set-up time for STOP condition
t BUF
for bus compatible masters
for bus devices
S
t
HD;STA
t LOW
SS
t r
to V
2
DD
C-bus.
; see
t
HD;DAT
Figure
Rev. 04 — 22 October 2004
Conditions
repeated start
t HIGH
9.
t f
t
SU;DAT
256
8-bit CMOS EEPROM with I
[1]
t
SU;STA
S
Min
0
4.7
4.0
4.7
4.0
4.7
5
0
250
4.0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
t
HD;STA
PCF85102C-2
Max
100
1
300
MBA705
2
C-bus interface
t
SU;STO
IL
Unit
kHz
ns
ns
ns
and V
s
s
s
s
s
s
s
s
P
11 of 20
IH