PCF85102C-2T/03,11 NXP Semiconductors, PCF85102C-2T/03,11 Datasheet - Page 7

• Manufacturer Part Number: PCF85102C-2T/03,11
• Description: IC EEPROM 2KBIT 100KHZ 8SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCF85102C-2T/03,11

• Memory Size: 2K (256 x 8)
• Package / Case: 8-SOIC (3.9mm Width)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 100kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 6.0 V
• Operating Temperature: -40°C ~ 85°C
• Organization: 256 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.1 MHz
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935262037118; PCF85102C2D-T; PCF85102C2D-T

Philips Semiconductors
9397 750 14216
Product data
8.1.3 Device addressing
8.1.4 Write operations
The master receiver must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge
clock pulse in such a way that the SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse.
Set-up and hold times must be taken into account. A master receiver must signal an
end of data to the slave transmitter by not generating an acknowledge on the last byte
that has been clocked out of the slave. In this event, the transmitter must leave the
data line HIGH to enable the master generation of the STOP condition.
Following a START condition, the bus master must output the address of the slave it
is accessing. The address of the PCF85102C-2 is shown in
power, no internal pull-up resistors are incorporated on the hardware selectable pins
and they must be connected to either V
The last bit of the slave address defines the operation to be performed. When set to
logic 1, a read operation is selected, while a logic 0 selects a write operation.
Byte/word write:
address field. This address field is a word address providing access to the 256 words
of memory. Upon receipt of the word address, the PCF85102C-2 responds with an
acknowledge and awaits the next eight bits of data, again responding with an
acknowledge. Word address is automatically incremented. The master can now
terminate the transfer by generating a STOP condition or transmit up to six more
bytes of data and then terminate by generating a STOP condition.
After this STOP condition, the E/W cycle starts and the bus is free for another
transmission. Its duration is 10 ms per byte.
During the E/W cycle the slave receiver does not send an acknowledge bit if
addressed via the I
Fig 4. Slave address.
Rev. 04 — 22 October 2004
For a write operation, the PCF85102C-2 requires a second
2
C-bus.
1
256
0
FIXED
1
8-bit CMOS EEPROM with I
DD
0
or V
SELECTABLE
A2
HARDWARE
SS
A1
.
A0 R/W
002aaa173
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
PCF85102C-2
Figure
4. To conserve
2
C-bus interface
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