PCF85102C-2T/03,11 NXP Semiconductors, PCF85102C-2T/03,11 Datasheet - Page 4

• Manufacturer Part Number: PCF85102C-2T/03,11
• Description: IC EEPROM 2KBIT 100KHZ 8SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCF85102C-2T/03,11

• Memory Size: 2K (256 x 8)
• Package / Case: 8-SOIC (3.9mm Width)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 100kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 6.0 V
• Operating Temperature: -40°C ~ 85°C
• Organization: 256 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.1 MHz
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935262037118; PCF85102C2D-T; PCF85102C2D-T

Philips Semiconductors
6. Pinning information
7. Device addressing
9397 750 14216
Product data
6.1 Pinning
6.2 Pin description
Table 4:
Table 5:
[1]
A2, A1, A0 are hardware selectable pins.
A system could have up to eight PCF85102C-2 devices on the same I
equivalent to a 16 kbit EEPROM or 8 pages of 256 bytes of memory.
The eight addresses are defined by the state of the A0, A1, A2 inputs (logic level ‘1’
when connected to V
various address combinations.
Symbol
A0
A1
A2
V
SDA
SCL
N.C.
V
Selection
Bit
Device
Fig 2. Pin configuration.
SS
DD
The Most Significant Bit (MSB) ‘b7’ is sent first.
Pin description
Device address code
b7
Pin
1
2
3
4
5
6
7
8
Rev. 04 — 22 October 2004
1
[1]
DD
, logic level ‘0’ when connected to GND).
Device code
b6
0
Description
address input 0
address input 1
address input 2
negative supply voltage
serial data input/output (I
serial clock input (I
no connect
positive supply voltage
V SS
A0
A1
A2
256
b5
1
2
3
4
1
8-bit CMOS EEPROM with I
002aaa248
b4
0
2
C-bus)
7
6
5
8
2
V DD
SDA
N.C.
SCL
C-bus)
A2
b3
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
PCF85102C-2
Chip Enable
A1
b2
Figure 3
2
C-bus interface
2
A0
b1
C-bus,
shows the
R/W
R/W
b0
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