MT28F004B5VG-8 TET TR Micron Technology Inc, MT28F004B5VG-8 TET TR Datasheet - Page 12

• Manufacturer Part Number: MT28F004B5VG-8 TET TR
• Description: IC FLASH 4MBIT 80NS 40TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT28F004B5VG-8 TET TR

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 4M (512K x 8)
• Speed: 80ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ISM STATUS REGISTER
to check for WRITE or ERASE completion or any
related errors. During or following a WRITE, ERASE or
ERASE SUSPEND, a READ operation outputs the sta-
tus register contents on DQ0–DQ7 without prior com-
mand. While the status register contents are read, the
outputs are not updated if there is a change in the ISM
status unless OE# or CE# is toggled. If the device is not
in the write, erase, erase suspend or status register read
mode, READ STATUS REGISTER (70h) can be issued to
view the status register contents.
the ISM and erase suspend status bits are reset by the
Table 2:
09005aef8075d1f1
MT28F004B5.fm - Rev. 4, Pub. 2/2004
STATUS
The 8-bit ISM status register (see Table 2) is polled
All of the defined bits are set by the ISM, but only
BIT #
SR0-2
SR7
SR6
SR5
SR4
SR3
STATUS REGISTER BIT
ISM STATUS
1 = Ready
0 = Busy
ERASE SUSPEND STATUS
1 = ERASE suspended
0 = ERASE in progress/completed
ERASE STATUS
1 = BLOCK ERASE error
0 = Successful BLOCK ERASE
WRITE STATUS
1 = WORD/BYTE WRITE error
0 = Successful WORD/BYTE WRITE
V
1 = No V
0 = V
RESERVED
PP
Status Register
STATUS
PP
present
PP
voltage detected
DESCRIPTION
The ISMS bit displays the active status of the state machine during
WRITE or BLOCK ERASE operations. The controlling logic polls this bit
to determine when the erase and write status bits are valid.
Issuing an ERASE SUSPEND places the ISM in the suspend mode and
sets this and the ISMS bit to “1.” The ESS bit remains “1” until an
ERASE RESUME is issued.
ES is set to “1” after the maximum number of ERASE cycles is executed
by the ISM without a successful verify. ES is only cleared by a CLEAR
STATUS REGISTER command or after a RESET.
WS is set to “1” after the maximum number of WRITE cycles is
executed by the ISM without a successful verify. WS is only cleared by a
CLEAR STATUS REGISTER command or after a RESET.
V
continuously, nor does it indicate a valid V
sampled for 5V after WRITE or ERASE CONFIRM is given. V
cleared by CLEAR STATUS REGISTER or by a RESET.
Reserved for future use.
SMART 5 BOOT BLOCK FLASH MEMORY
PP
S detects the presence of a V
12
ISM. The erase, write and V
cleared using CLEAR STATUS REGISTER. If the Vpp
status bit (SR3) is set, the CEL does not allow further
WRITE or ERASE operations until the status register is
cleared. This enables the user to choose when to poll
and clear the status register. For example, the host sys-
tem may perform multiple BYTE WRITE operations
before checking the status register instead of checking
after each individual WRITE. Asserting the RP# signal
or powering down the device also clears the status
register.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PP
voltage. It does not monitor V
PP
voltage. The V
PP
status bits must be
©2002 Micron Technology, Inc.
PP
PP
S must be
4Mb
pin is
PP