MT28F004B5VG-8 TET TR Micron Technology Inc, MT28F004B5VG-8 TET TR Datasheet - Page 13

• Manufacturer Part Number: MT28F004B5VG-8 TET TR
• Description: IC FLASH 4MBIT 80NS 40TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT28F004B5VG-8 TET TR

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 4M (512K x 8)
• Speed: 80ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

COMMAND EXECUTION
ferent operational modes. Each mode allows specific
operations to be performed. Several modes require a
sequence of commands to be written before they are
reached. The following section describes the proper-
ties of each mode, and Table 3 lists all command
sequences required to perform the desired operation.
Read Array
upon power-up and after a RESET. If the device is in
any other mode, READ ARRAY (FFh) must be given to
return to the array read mode. Unlike the WRITE
SETUP command (40h), READ ARRAY does not need
to be given before each individual read access.
Identify Device
to enter the identify device mode. While the device is
in this mode, any READ produces the device ID when
A0 is HIGH and manufacturer compatibility ID when
A0 is LOW. The device remains in this mode until
another command is given.
WRITE Sequence
the array. WRITE SETUP (40h or 10h) is given in the
Table 3:
Notes: 1. Must follow WRITE or ERASE CONFIRM commands to the CEL to enable Flash array READ cycles.
09005aef8075d1f1
MT28F004B5.fm - Rev. 4, Pub. 2/2004
COMMANDS
READ ARRAY
IDENTIFY DEVICE
READ STATUS REGISTER
CLEAR STATUS REGISTER
ERASE SETUP/CONFIRM
ERASE SUSPEND/RESUME
WRITE SETUP/WRITE
ALTERNATE WORD/BYTE
WRITE
Commands are issued to bring the device into dif-
The array read mode is the initial state of the device
IDENTIFY DEVICE (90h) may be written to the CEL
Two consecutive cycles are needed to write data to
2. IA = Identify Address: 00h for manufacturer compatibility ID; 01h for device ID.
3. ID = Identify Data.
4. SRD = Status Register Data.
5. On x16 (X00) devices BA = Block Address (A12–A17), on x8 (00X) devices BA = Block Address (A13–A18).
6. Addresses are “Don’t Care” in first cycle but must be held stable.
7. WA = Address to be written; WD = Data to be written to WA.
Command Sequences
CYCLES
REQ’D
BUS
1
3
2
1
2
2
2
2
OPERATION
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
FIRST CYCLE
SMART 5 BOOT BLOCK FLASH MEMORY
ADDRESS
13
X
X
X
X
X
X
X
X
first cycle. The next cycle is the WRITE, during which
the write address and data are issued and V
brought to V
requires that the RP# pin be brought to V
WP# pin be brought HIGH at the same time V
brought to V
word or byte. V
is completed (SR7 = 1).
bit (SR7) is at “0,” and the device does not respond to
any commands. Any READ operation produces the
status register contents on DQ0–DQ7. When the ISM
status bit (SR7) is set to a logic 1, the write is complete,
and the device goes into the status register read mode
until another command is given.
aborted except by a RESET or by powering down the
part. Doing either during a WRITE corrupts the data
being written. If only the WRITE SETUP command has
been given, the WRITE may be nullified by performing
a null WRITE. To execute a null WRITE, FFh must be
written when BYTE# is LOW, or FFFFh must be written
when BYTE# is HIGH. When the ISM status bit (SR7) is
set, the device is in the status register read mode until
another command is issued.
While the ISM executes the WRITE, the ISM status
After the ISM has initiated the WRITE, it cannot be
DATA OPERATION
Micron Technology, Inc., reserves the right to change products or specifications without notice.
B0h
90h
70h
50h
20h
40h
10h
FFh
PPH
PPH
PP
WRITE
WRITE
WRITE
WRITE
READ
READ
. The ISM will now begin to write the
. Writing to the boot block also
must be held at V
SECOND CYCLE
ADDRESS
WA
WA
BA
IA
X
X
PPH
©2002 Micron Technology, Inc.
DATA
until the write
HH
SRD
D0h
D0h
WD
WD
ID
or that the
4Mb
NOTES
2, 3
5, 6
6, 7
6, 7
PP
PP IS
1
4
is