MT28F004B5VG-8 TET TR Micron Technology Inc, MT28F004B5VG-8 TET TR Datasheet - Page 4

• Manufacturer Part Number: MT28F004B5VG-8 TET TR
• Description: IC FLASH 4MBIT 80NS 40TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT28F004B5VG-8 TET TR

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 4M (512K x 8)
• Speed: 80ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIN DESCRIPTIONS
09005aef8075d1f1
MT28F004B5.fm - Rev. 4, Pub. 2/2004
44-PIN SOP
36, 35, 34, 3
11, 10, 9, 8,
NUMBERS
42, 41, 40,
39, 38, 37,
15, 17, 19,
21, 24, 26,
16, 18, 20,
22, 25, 27,
7, 6, 5, 4,
28, 30
13, 32
43
12
44
14
33
31
23
29
2
1
–
25-28, 32-35
16,15, 14, 8,
NUMBERS
21, 20, 19,
7, 36, 6, 5,
29, 37, 38
4, 3, 2, 1,
40-PIN
18, 17,
40, 13
30, 31
23, 39
TSOP
12
22
10
24
11
9
–
–
–
9, 10, 15, 16
19, 18, 8, 7,
6, 5, 4, 3, 2,
NUMBERS
25, 24, 23,
22, 21, 20,
29, 31, 33,
35, 38, 40,
30, 32, 34,
36, 39, 41,
1, 48, 17
48-PIN
27, 46
42, 44
TSOP
11
14
47
45
43
13
37
26
12
28
DQ0–DQ7
SYMBOL
A0–A17/
BYTE#
DQ15
DQ8–
DQ14
(A18)
(A-1)
WE#
WP#
OE#
CE#
RP#
V
V
V
NC
PP
CC
SS
SMART 5 BOOT BLOCK FLASH MEMORY
Output
Output
Output
Supply
Supply
Supply
Input/
Input/
Input/
TYPE
Input
Input
Input
Input
Input
Input
Input
–
4
Write Enable: Determines if a given cycle is a WRITE cycle.
If WE# is LOW, the cycle is either a WRITE to the command
execution logic (CEL) or to the memory array.
Write Protect: Unlocks the boot block when HIGH if V
5V and RP# = V
WRITE or ERASE operation on other blocks.
Chip Enable: Activates the device when LOW. When CE# is
HIGH, the device is disabled and goes into standby power
mode.
Reset/Power-Down: When LOW, RP# clears the status
register, sets the internal state machine (ISM) to the array
read mode and places the device in deep power-down
mode. All inputs, including CE#, are “Don’t Care,” and all
outputs are High-Z. RP# unlocks the boot block and
overrides the condition of WP# when at V
held at V
Output Enable: Enables data output buffers when LOW.
When OE# is HIGH, the output buffers are disabled.
Byte Enable: If BYTE# = HIGH, the upper byte is active
through DQ8–DQ15. If BYTE# = LOW, DQ8–DQ14 are
High-Z, and all data is accessed through DQ0–DQ7. DQ15/
(A-1) becomes the least significant address input.
Address Inputs: Select a unique, 16-bit word or 8-bit byte.
The Q15/(A-1) input becomes the lowest order address
when BYTE# = LOW (MT28F400B5) to allow for a selection
of an 8-bit byte from the 524,288 available.
Data I/O: MSB of data when BYTE# = HIGH. Address Input:
LSB of address input when BYTE# = LOW during READ or
WRITE operation.
Data I/Os: Data output pins during any READ operation or
data input pins during a WRITE. These pins are used to
input commands to the CEL.
Data I/Os: Data output pins during any READ operation or
data input pins during a WRITE when BYTE# = HIGH. These
pins are High-Z when BYTE# is LOW.
Write/Erase Supply Voltage: From a WRITE or ERASE
CONFIRM until completion of the WRITE or ERASE, V
must be at V
operations.
Power Supply: +5V ±10%.
Ground.
No Connect: These pins may be driven or left unconnected.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
during all other modes of operation.
PPH
IH
(5V). V
during a WRITE or ERASE. Does not affect
DESCRIPTION
PP
= “Don’t Care” during all other
HH
©2002 Micron Technology, Inc.
, and must be
4Mb
PP
PP
=