MT28F004B5VG-8 TET TR Micron Technology Inc, MT28F004B5VG-8 TET TR Datasheet - Page 7

• Manufacturer Part Number: MT28F004B5VG-8 TET TR
• Description: IC FLASH 4MBIT 80NS 40TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT28F004B5VG-8 TET TR

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 4M (512K x 8)
• Speed: 80ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FUNCTIONAL DESCRIPTION
ries incorporate a number of features ideally suited for
system firmware. The memory array is segmented into
individual erase blocks. Each block may be erased
without affecting data stored in other blocks. These
memory blocks are read, written and erased with com-
mands to the command execution logic (CEL). The
CEL controls the operation of the internal state
machine (ISM), which completely controls all WRITE,
BLOCK ERASE, and VERIFY operations. The ISM pro-
tects each memory location from over-erasure and
optimizes each memory location for maximum data
retention. In addition, the ISM greatly simplifies the
control necessary for writing the device in-system or in
an external programmer.
mation on the operation of the MT28F004B5 and
MT28F400B5 and is organized into these sections:
OVERVIEW
Smart 5 Technology (B5)
in-system READ, WRITE and ERASE operations. For
5V-only systems, WRITE and ERASE operations may be
executed with a V
nology advances, 5V V
production programming.
Seven Independently Erasable
Memory Blocks
into seven independently erasable memory blocks that
allow portions of the memory to be erased without
affecting the rest of the memory data. A special boot
block is hardware-protected against inadvertent era-
sure or writing by requiring either a super-voltage on
the RP# pin or driving the WP# pin HIGH. One of these
two conditions must exist, along with the V
09005aef8075d1f1
MT28F004B5.fm - Rev. 4, Pub. 2/2004
The MT28F004B5 and MT28F400B5 Flash memo-
The Functional Description provides detailed infor-
• Overview
• Memory Architecture
• Output (READ) operations
• Input Operations
• Command Set
• ISM Status Register
• Command Execution
• Error Handling
• WRITE/ERASE Cycle Endurance
• Power Usage
• Power-Up
Smart 5 technology allows maximum flexibility for
The MT28F004B5 and MT28F400B5 are organized
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voltage of 5V. Due to process tech-
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is optimal for application and
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voltage
SMART 5 BOOT BLOCK FLASH MEMORY
7
(5V) on the V
performed on the boot block. The remaining blocks
require that only the V
pin before writing or erasing.
Hardware-Protected Boot
written only when the RP# pin is taken to V
the WP# pin is brought HIGH. This provides additional
security for the core firmware during in-system firm-
ware updates should an unintentional power fluctua-
tion or system reset occur. The MT28F004B5 and
MT28F400B5 are available with the boot block starting
at the bottom of the address space (“B” suffix) or the
top of the address space (“T” suffix).
Selectable Bus Size (MT28F400B5 only)
x 8) or 16-bit (256K x 16) data bus for reading and writ-
ing the memory. The BYTE# pin is used to select the
bus width. In the x16 configuration, control data is
read or written only on the lower eight bits (DQ0–
DQ7).
data pins for the selected configuration. When the x8
configuration is selected, data is written in byte form;
when the x16 configuration is selected, data is written
in word form.
Internal State Machine (ISM)
fied with an ISM that controls all erase and write algo-
rithms in the memory array. The ISM ensures
protection against overerasure and optimizes write
margin to each cell.
increments and monitors WRITE attempts, verifies
write margin on each memory cell and updates the
ISM status register. When BLOCK ERASE is performed,
the ISM automatically overwrites the entire addressed
block (eliminates overerasure), increments and moni-
tors ERASE attempts, and sets bits in the ISM status
register.
ISM Status Register
sor to monitor the status of the ISM during WRITE and
ERASE operations. Two bits of the 8-bit status register
are set and cleared entirely by the ISM. These bits indi-
cate whether the ISM is busy with a WRITE or ERASE
task and when an ERASE has been suspended. Addi-
This block of the memory array can be erased or
The MT28F400B5 allows selection of an 8-bit (512K
Data written to the memory array utilizes all active
Block erase and byte/word write timing are simpli-
During WRITE operations, the ISM automatically
The ISM status register enables an external proces-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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pin, before a WRITE or ERASE will be
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voltage be present on the V
©2002 Micron Technology, Inc.
HH
4Mb
or when
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