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MT48V8M16LFB4-10:G
MT48V8M16LFB4-10:G | |
|---|---|
| Manufacturer Part Number | MT48V8M16LFB4-10:G |
| Description | IC SDRAM 128MBIT 100MHZ 54VFBGA |
| Manufacturer | Micron Technology Inc |
| MT48V8M16LFB4-10:G datasheets |
|
Availability: By request
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Warranty: 60 days
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Specifications of MT48V8M16LFB4-10:G | |||
|---|---|---|---|
| Format - Memory | RAM | Memory Type | Mobile SDRAM |
| Memory Size | 128M (8Mx16) | Speed | 100MHz |
| Interface | Parallel | Voltage - Supply | 2.3 V ~ 2.7 V |
| Operating Temperature | 0°C ~ 70°C | Package / Case | 54-VFBGA |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
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Upon completion of a burst, assuming no other commands have been initiated, the DQ
will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it
will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a subsequent READ command, and
data from a fixed-length READ burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst either follows the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ
command should be issued x cycles before the clock edge at which the last desired data
element is valid, where x = CL - 1.
Figure 13:
CAS Latency
CLK
COMMAND
CLK
COMMAND
CLK
COMMAND
This is shown in Figure 14 on page 29 for CL = 2 and CL = 3; data element n + 3 is either
the last of a burst of four or the last desired of a longer burst. The 128Mb SDRAM uses a
pipelined architecture and, therefore, does not require the 2n rule associated with a
prefetch architecture. A READ command can be initiated on any clock cycle following a
previous READ command. Full-speed random read accesses can be performed to the
same bank, as shown in Figure 15 on page 30, or each subsequent READ may be
performed to a different bank.
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
T0
T1
T2
READ
NOP
t
t OH
LZ
D
DQ
OUT
t AC
CL = 1
T0
T1
T2
READ
NOP
NOP
t
LZ
DQ
t AC
CL = 2
T0
T1
T2
READ
NOP
NOP
DQ
CL = 3
28
128Mb: x16, x32 Mobile SDRAM
T3
t OH
D
OUT
T3
T4
NOP
t
t OH
LZ
D
OUT
t AC
DON’T CARE
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
READs
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