M29W640FT70ZA6E NUMONYX, M29W640FT70ZA6E Datasheet - Page 15

• Manufacturer Part Number: M29W640FT70ZA6E
• Description: IC FLASH 64MBIT 70NS 48TFBGA
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29W640FT70ZA6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 64M (8Mx8, 4Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TFBGA
• Package: 48TFBGA
• Cell Type: NOR
• Density: 64 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Top
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 127
• Timing Type: Asynchronous
• Interface Type: Parallel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5034; 497-5034

3
3.1
3.2
3.3
3.4
Bus operations
There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby. See
= V
than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus
operations.
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V
Enable High, V
AC
becomes valid.
Bus Write
Bus Write operations write to the Command Interface. To speed up the read operation the
memory array can be read in Page mode where data is internally read and stored in a page
buffer. The Page has a size of 4 Words and is addressed by the address inputs A0-A1.
A valid Bus Write operation begins by setting the desired address on the Address Inputs.
The Address Inputs are latched by the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the
Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs
first. Output Enable must remain High, V
Figure 10: Write AC waveforms, Write Enable
Chip Enable
Table 16: Write AC characteristics, Chip Enable
requirements.
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V
Standby
When Chip Enable is High, V
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to
the Standby Supply Current, I
Standby current level see
During program or erase operations the memory will continue to use the Program/Erase
Supply Current, I
IL
waveforms, and
and
Table 5: Bus operations, BYTE = V
controlled, and
IH
. The Data Inputs/Outputs will output the value, see
CC3
Table 14: Read AC
, for Program or Erase operations until the operation completes.
Table 13: DC
Table 15: Write AC characteristics, Write Enable controlled
IH
CC2
, the memory enters Standby mode and the Data
IL
, Chip Enable should be held within V
, to Chip Enable and Output Enable and keeping Write
characteristics.
characteristics, for details of when the output
IH
, during the whole Bus Write operation. See
IH
controlled,
, for a summary. Typically glitches of less
controlled, for details of the timing
Figure 11: Write AC waveforms,
Table 4: Bus operations, BYTE
Figure 8: Read Mode
CC
± 0.2V. For the
15/71
and
IH
.