M29W640FT70ZA6E NUMONYX, M29W640FT70ZA6E Datasheet - Page 23

• Manufacturer Part Number: M29W640FT70ZA6E
• Description: IC FLASH 64MBIT 70NS 48TFBGA
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29W640FT70ZA6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 64M (8Mx8, 4Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TFBGA
• Package: 48TFBGA
• Cell Type: NOR
• Density: 64 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Top
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 127
• Timing Type: Asynchronous
• Interface Type: Parallel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5034; 497-5034

4.2
4.2.1
4.2.2
1. For devices with process technology code “H” in the marking, the Quadruple Byte Program command can be performed
without applying V
Fast Program commands
There are four Fast Program commands available to improve the programming throughput,
by writing several adjacent words or bytes in parallel. The Double, Quadruple and Octuple
Byte Program commands are available for x8 operations, while the Double Quadruple Word
Program command are available for x16 operations.
Fast Program commands can be suspended and then resumed by issuing a Program
Suspend command and a Program Resume command, respectively (see
Program Suspend command
To perform some of the Fast Program commands, V
Care must be taken because applying a V
any protected block.
Double Byte Program command
The Double Byte Program command is used to write a page of two adjacent Bytes in
parallel. The two bytes must differ only in DQ15A-1. Three bus write cycles are necessary to
issue the Double Byte Program command.
1.
2.
3.
Quadruple Byte Program command
The Quadruple Byte Program command is used to write a page of four adjacent Bytes in
parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles
are necessary to issue the Quadruple Byte Program command.
1.
2.
3.
4.
5.
The first bus cycle sets up the Double Byte Program Command.
The second bus cycle latches the Address and the Data of the first byte to be written.
The third bus cycle latches the Address and the Data of the second byte to be written.
The first bus cycle sets up the Quadruple Byte Program Command.
The second bus cycle latches the Address and the Data of the first byte to be written.
The third bus cycle latches the Address and the Data of the second byte to be written.
The fourth bus cycle latches the Address and the Data of the third byte to be written.
The fifth bus cycle latches the Address and the Data of the fourth byte to be written and
starts the Program/Erase Controller.
PPH
on the V
PP
/WP pin. For other devices, applying V
and
Section 4.1.9: Program Resume
PPH
(1)
to the V
PPH
on the V
PPH
PP
must be applied to V
/WP pin will temporarily unprotect
PP
/WP pin is mandatory.
command).
Section 4.1.8:
PP
/WP pin.
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