ISL94200IRZ Intersil, ISL94200IRZ Datasheet - Page 22

• Manufacturer Part Number: ISL94200IRZ
• Description: IC MULTI LI-ION OC PROT 24-QFN
• Manufacturer: Intersil

Specifications of ISL94200IRZ

• Function: Over/Under Voltage Protection
• Battery Type: Lithium-Ion (Li-Ion)
• Voltage - Supply: 5 V ~ 10 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In the read mode, the device transmits eight bits of data,
releases the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will
continues to transmit data. The device terminates further
data transmissions if an acknowledge is not detected. The
master must then issue a stop condition to return the device
to Standby mode and place the device into a known state
.
WRITE OPERATIONS
For a write operation, the device requires a slave byte and
an address byte. The slave byte specifies the particular
device on the I
address specifies one of the registers in that device. After
receipt of each byte, the device responds with an
acknowledge, and awaits the next eight bits from the master.
After the acknowledge, following the transfer of data, the
master terminates the transfer by generating a stop
condition. See Figure 11.
FROM RECEIVER
FIGURE 10. ACKNOWLEDGE RESPONSE FROM RECEIVER
TRANSMITTER
SCL
SDA
DATA OUTPUT
DATA OUTPUT
SDA
SCL
SCL FROM
MASTER
FIGURE 8. VALID DATA CHANGES ON I
FROM
FIGURE 9. I
2
STABLE
START
C bus that the master is writing to. The
DATA
START
2
C START AND STOP BITS
1
CHANGE
22
DATA
STABLE
DATA
8
STOP
ACKNOWLEDGE
2
C BUS
9
ISL94200
When receiving data from the master, the value in the data
byte is transferred into the register specified by the address
byte on the falling edge of the clock following the 8th data bit.
After receiving the acknowledge after the data byte, the
device automatically increments the address. So, before
sending the stop bit, the master may send additional data to
the device without re-sending the slave and address bytes.
After writing to address 0AH, the address “wraps around” to
address 0. Do not continue to write to addresses higher than
address 08H, since these addresses access registers that
are reserved. Writing to these locations can result in
unexpected device operation.
Read Operations
Read operations are initiated in the same manner as write
operations with the host sending the address where the read
is to start (but no data). Then, the host sends an ACK, a
repeated start, and the slave byte with the LSB = 1. After the
device acknowledges the slave byte, the device sends out
one bit of data for each master clock. After the slave sends
eight bits to the master, the master sends a NACK (Not
acknowledge) to the device, to indicate the data transfer is
complete, then the master sends a stop bit. See Figure 12.
After sending the eighth data bit to the master, the device
automatically increments its internal address pointer. So the
master, instead of sending a NACK and the stop bit, can
send additional clocks to read the contents of the next
register - without sending another slave and address byte.
If the last address read or written is known, the master can
initiate a current address read. In this case, only the slave
byte is sent before data is returned. (See Figure 12.)
.
Register Protection
The Discharge Set, Charge Set, and Feature Set
configuration registers are write protected on initial power
up. In order to write to these registers it is necessary to set a
bit to enable each one. These write enable bits are in the
Write Enable register (Address 08H).
Write the FSETEN bit (Addr 8:bit 7) to “1” to enable changes
to the data in the Feature Set register (Address 7).
SDA BUS
A
R
S
T
T
0 1 0 1
FIGURE 11. WRITE SEQUENCE
SLAVE
BYTE
0
0 0
ISL94200: SLAVE BYTE = 50H
0
A
C
K
REGISTER
ADDRESS
A
C
K
DATA
July 3, 2008
FN6718.0
A
C
K
S
O
P
T