MAX15048ETJ+  

Manufacturer Part Number  MAX15048ETJ+ 
Description  IC CTRLR PWM STPDN TRIPL 32WQFN 
Manufacturer  Maxim Integrated Products 
MAX15048ETJ+ datasheet 

Specifications of MAX15048ETJ+  

Applications  Power Supply Controller, Sequencer  Voltage  Supply  4.7 V ~ 23 V 
Current  Supply  6mA  Operating Temperature  40°C ~ 85°C 
Mounting Type  Surface Mount  Package / Case  32WQFN Exposed Pad 
Number Of Outputs  3  Output Voltage  5 V 
Input Voltage  4.7 V to 23 V  Supply Current  6 mA 
Switching Frequency  200 KHz  Mounting Style  SMD/SMT 
Maximum Operating Temperature  + 85 C  Minimum Operating Temperature   40 C 
Lead Free Status / RoHS Status  Lead free / RoHS Compliant  Voltage  Input   
PrevNext
TripleOutput Buck Controllers
with Tracking/Sequencing
(f
) is programmable between 200kHz and 1.2MHz
SW
(see the Setting the Switching Frequency section). The
peaktopeak inductor current (DI
the peaktopeak output ripple, is worst at the maximum
input voltage. See the OutputCapacitor Selection sec
tion to verify that the worstcase output current ripple is
acceptable. The inductor saturation current (I
important to avoid runaway current during continuous
output shortcircuit conditions. Select an inductor with an
I
specification higher than the maximum peak cur
SAT
rent. Inductor parasitic resistance (DCR) causes copper
losses and affects efficiency. Select a lowloss inductor
having the lowest possible DCR that fits in the allocated
dimensions.
InputCapacitor Selection
The discontinuous input current of the buck converter
causes large inputripple currents, and therefore, the
input capacitor must be carefully chosen to withstand
the inputripple current and keep the inputvoltage
ripple within design requirements. The 120° ripple phase
operation increases the frequency of the input capacitor
ripple current to thrice the individual converter switching
frequency. When using ripple phasing, the worstcase
inputcapacitor ripple current is when only one converter
with the highest output current is on.
The inputvoltage ripple comprises DV
capacitor discharge) and DV
(caused by the ESR of
ESR
the input capacitor). The total voltage ripple is the sum of
and DV
, which peaks at the end of the on cycle.
Q
ESR
DV
Calculate the input capacitance and ESR required for a
specified ripple using the following equations:
∆
V
ESR
=
ESR
+
I
LOAD(MAX)
V
×
I
LOAD(MAX)
=
C
IN
(
∆
+
V
f
Q
SW
where:
(
)
V
 V
×
IN
OUT_
∆
=
I
PP
V
×
f
IN
SW
I
is the maximum output current, DI
LOAD(MAX)
peaktopeak inductor current, and f
frequency.
20
_____________________________________________________________________________________
For the condition with only one converter on, calculate
the inputripple current using the following equation:
), which reflects
PP
I
CIN(RMS)
) is also
SAT
The MAX15048/MAX15049 include UVLO hysteresis to
avoid possible unintentional chattering during turnon.
Use additional bulk capacitance if the input source
impedance is high. At lower input voltage, additional
input capacitance helps avoid possible undershoot
below the UVLO threshold during transient loading.
The allowed outputvoltage ripple and the maximum
deviation of the output voltage during load steps deter
mine the required output capacitance and its ESR. The
steadystate output ripple is mainly composed of DV
(caused by the capacitor discharge) and DV
by the voltage drop across the ESR of the output capaci
tor). The equations for calculating the output capaci
tance and its ESR are:
(caused by the
Q
and DV
ESR
DV
out of phase from each other. If using ceramic capaci
tors, which generally have low ESR, DV
using electrolytic capacitors, DV
∆
I
PP
The allowable deviation of the output voltage during fast
2
load transients also affects the output capacitance, its
OUT_
ESR, and its ESL. The output capacitor supplies the load
V
current during a load step until the controller responds
IN
)
with a greater duty cycle. The response time (t
depends on the gain bandwidth of the converter (see the
Compensation Design Guidelines section). The resistive
drop across the output capacitor’s ESR, the drop across
V
OUT_
the capacitor’s ESL, and the capacitor discharge causes
×
L
a voltage droop during the loadstep (I
bination of lowESR tantalum/aluminum electrolytic and
ceramic capacitors for better loadtransient and voltage
is the
PP
ripple performance. Nonleaded capacitors and capaci
is the switching
SW
tors in parallel help reduce the ESL. Keep the maximum
outputvoltage deviation below the tolerable limits of the
electronics being powered.
(
V
×
V
 V
OUT_
IN
OUT_
=
I
×
LOAD(MAX)
V
IN
OutputCapacitor Selection
(caused
ESR
∆
I
PP
C
=
OUT
8
× ∆
V
×
f
Q
SW
∆
V
ESR
=
ESR
∆
I
PP
are not directly additive since they are
Q
dominates. If
Q
dominates.
ESR
RESPONSE
). Use a com
STEP
)
Q
)
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