IC CTRLR PWM STP-DN TRIPL 32WQFN

MAX15048ETJ+

Manufacturer Part NumberMAX15048ETJ+
DescriptionIC CTRLR PWM STP-DN TRIPL 32WQFN
ManufacturerMaxim Integrated Products
MAX15048ETJ+ datasheet
 


Specifications of MAX15048ETJ+

ApplicationsPower Supply Controller, SequencerVoltage - Supply4.7 V ~ 23 V
Current - Supply6mAOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case32-WQFN Exposed Pad
Number Of Outputs3Output Voltage5 V
Input Voltage4.7 V to 23 VSupply Current6 mA
Switching Frequency200 KHzMounting StyleSMD/SMT
Maximum Operating Temperature+ 85 CMinimum Operating Temperature- 40 C
Lead Free Status / RoHS StatusLead free / RoHS CompliantVoltage - Input-
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Triple-Output Buck Controllers
with Tracking/Sequencing
(f
) is programmable between 200kHz and 1.2MHz
SW
(see the Setting the Switching Frequency section). The
peak-to-peak inductor current (DI
the peak-to-peak output ripple, is worst at the maximum
input voltage. See the Output-Capacitor Selection sec-
tion to verify that the worst-case output current ripple is
acceptable. The inductor saturation current (I
important to avoid runaway current during continuous
output short-circuit conditions. Select an inductor with an
I
specification higher than the maximum peak cur-
SAT
rent. Inductor parasitic resistance (DCR) causes copper
losses and affects efficiency. Select a low-loss inductor
having the lowest possible DCR that fits in the allocated
dimensions.
Input-Capacitor Selection
The discontinuous input current of the buck converter
causes large input-ripple currents, and therefore, the
input capacitor must be carefully chosen to withstand
the input-ripple current and keep the input-voltage
ripple within design requirements. The 120° ripple phase
operation increases the frequency of the input capacitor
ripple current to thrice the individual converter switching
frequency. When using ripple phasing, the worst-case
input-capacitor ripple current is when only one converter
with the highest output current is on.
The input-voltage ripple comprises DV
capacitor discharge) and DV
(caused by the ESR of
ESR
the input capacitor). The total voltage ripple is the sum of
and DV
, which peaks at the end of the on cycle.
Q
ESR
DV
Calculate the input capacitance and ESR required for a
specified ripple using the following equations:
V
ESR
=
ESR
+
I
LOAD(MAX)
V
× 
I
LOAD(MAX)
=
C
IN
(
+
V
f
Q
SW
where:
(
)
V
- V
×
IN
OUT_
=
I
P-P
V
×
f
IN
SW
I
is the maximum output current, DI
LOAD(MAX)
peak-to-peak inductor current, and f
frequency.
20
_____________________________________________________________________________________
For the condition with only one converter on, calculate
the input-ripple current using the following equation:
), which reflects
P-P
I
CIN(RMS)
) is also
SAT
The MAX15048/MAX15049 include UVLO hysteresis to
avoid possible unintentional chattering during turn-on.
Use additional bulk capacitance if the input source
impedance is high. At lower input voltage, additional
input capacitance helps avoid possible undershoot
below the UVLO threshold during transient loading.
The allowed output-voltage ripple and the maximum
deviation of the output voltage during load steps deter-
mine the required output capacitance and its ESR. The
steady-state output ripple is mainly composed of DV
(caused by the capacitor discharge) and DV
by the voltage drop across the ESR of the output capaci-
tor). The equations for calculating the output capaci-
tance and its ESR are:
(caused by the
Q
and DV
ESR
DV
out of phase from each other. If using ceramic capaci-
tors, which generally have low ESR, DV
using electrolytic capacitors, DV
I
P-P
The allowable deviation of the output voltage during fast-
2
load transients also affects the output capacitance, its
OUT_
ESR, and its ESL. The output capacitor supplies the load
V
current during a load step until the controller responds
IN
)
with a greater duty cycle. The response time (t
depends on the gain bandwidth of the converter (see the
Compensation Design Guidelines section). The resistive
drop across the output capacitor’s ESR, the drop across
V
OUT_
the capacitor’s ESL, and the capacitor discharge causes
×
L
a voltage droop during the load-step (I
bination of low-ESR tantalum/aluminum electrolytic and
ceramic capacitors for better load-transient and voltage-
is the
P-P
ripple performance. Nonleaded capacitors and capaci-
is the switching
SW
tors in parallel help reduce the ESL. Keep the maximum
output-voltage deviation below the tolerable limits of the
electronics being powered.
(
V
×
V
- V
OUT_
IN
OUT_
=
I
×
LOAD(MAX)
V
IN
Output-Capacitor Selection
(caused
ESR
I
P-P
C
=
OUT
8
× ∆
V
×
f
Q
SW
V
ESR
=
ESR
I
P-P
are not directly additive since they are
Q
dominates. If
Q
dominates.
ESR
RESPONSE
). Use a com-
STEP
)
Q
)