IC CTRLR PWM STP-DN TRIPL 32WQFN

MAX15048ETJ+

Manufacturer Part NumberMAX15048ETJ+
DescriptionIC CTRLR PWM STP-DN TRIPL 32WQFN
ManufacturerMaxim Integrated Products
MAX15048ETJ+ datasheet
 


Specifications of MAX15048ETJ+

ApplicationsPower Supply Controller, SequencerVoltage - Supply4.7 V ~ 23 V
Current - Supply6mAOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case32-WQFN Exposed Pad
Number Of Outputs3Output Voltage5 V
Input Voltage4.7 V to 23 VSupply Current6 mA
Switching Frequency200 KHzMounting StyleSMD/SMT
Maximum Operating Temperature+ 85 CMinimum Operating Temperature- 40 C
Lead Free Status / RoHS StatusLead free / RoHS CompliantVoltage - Input-
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Design procedures for both Type II and Type III compen-
sators are shown below.
Type II: Compensation when f
CO
When the f
is lower than f
ZERO, ESR
a Type II compensation network provides the neces-
sary closed-loop response. The Type II compensation
network provides a midband compensating zero and
high-frequency pole (see Figures 5a and 5b).
R
C
provides the midband zero f
F
F
MID, ZERO
provides the high-frequency pole. Use the following proce-
dure to calculate the compensation network components:
1) Calculate the f
and LC double pole, f
ZERO, ESR
=
f
ZERO, ESR
π ×
2
ESR C
1
f
=
LC
2
π ×
L C
×
V
OUT_
R
1
g
M
V
REF
R
2
R
F
C
F
Figure 5a. Type II Compensation Network
GAIN
(dB)
1ST ASYMPTOTE
G
V
V
OUT_ -1
(ωC
)
-1
MOD
REF
F
3RD ASYMPTOTE
2ND ASYMPTOTE
OUT_ -1
G
V
V
OUT_ -1
G
V
V
RF
MOD
REF
MOD
REF
1ST POLE
1ST ZERO
(AT ORIGIN)
(R
C
)
-1
F
F
Figure 5b. Type II Compensation Network Response
______________________________________________________________________________________
Triple-Output Buck Controllers
with Tracking/Sequencing
2) Select the unity-gain crossover frequency as:
> f
ZERO, ESR
and close to f
,
CO
LC
3) Determine R
, and R
C
F
CF
Note: R
F
over frequency to unity, e.g., G
:
LC
= 1V/V. The transconductance error-amplifier gain is
1
G
(f
E/A
CO
×
OUT
G
MOD CO
OUT
The total loop gain can be expressed logarithmically as
follows:
[
20 log
×
10
COMP_
where V
RAMP
to 1.2V:
4) Place a zero at or below the LC double pole, f
C
CF
5) Place a high-frequency pole at or below f
6) Choose an appropriately sized R
OUT_ to FB_, start with a 10kI). Once R
calculate R
-1
(ωC
)
CF
where V
FB_
ω(rad/s)
2ND POLE
(R
C
)
-1
F
CF
f
SW
f
CO
10
from the following:
F
V
(2
π ×
f
×
L) V
RAMP
OUT_
CO
=
R
F
V
×
V
×
g
×
ESR
FB_
IN
MOD
is derived by setting the total loop gain at cross-
(f
) x G
E/A
CO
) = g
x R
, while the modulator gain is:
MOD
F
V
ESR
IN
=
×
×
(f
)
V
2
π ×
f
×
L
RAMP
CO
×
×
ESR V
V
IN
FB_
]
g R
+
20 log
×
M F
10
(2
× π ×
f
×
L) V
×
×
CO
OUT_
is the peak-to-peak ramp amplitude equal
1
C
=
F
π ×
×
2
R
f
F
LC
P
1
=
C
CF
π ×
R
×
f
F
SW
(connected from
1
using the following equation:
2
V
FB_
R
=
R
×
2
1
V
- V
OUT_
FB_
= 0.6V.
(f
)
MOD
CO
V
FB_
V
OUT_
=
0dB
V
RAMP
:
LC
= 0.5 x f
:
SW
is selected,
1
25