IC CTRLR PWM STP-DN TRIPL 32WQFN

MAX15048ETJ+

Manufacturer Part NumberMAX15048ETJ+
DescriptionIC CTRLR PWM STP-DN TRIPL 32WQFN
ManufacturerMaxim Integrated Products
MAX15048ETJ+ datasheet
 


Specifications of MAX15048ETJ+

ApplicationsPower Supply Controller, SequencerVoltage - Supply4.7 V ~ 23 V
Current - Supply6mAOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case32-WQFN Exposed Pad
Number Of Outputs3Output Voltage5 V
Input Voltage4.7 V to 23 VSupply Current6 mA
Switching Frequency200 KHzMounting StyleSMD/SMT
Maximum Operating Temperature+ 85 CMinimum Operating Temperature- 40 C
Lead Free Status / RoHS StatusLead free / RoHS CompliantVoltage - Input-
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Use the following equations to calculate the required
ESR, ESL, and capacitance value during a load step:
V
ESR
=
ESR
I
STEP
I
×
t
RESPONSE
STEP
C
=
OUT
V
Q
V
×
t
ESL
STEP
ESL
=
I
STEP
1
=
t
RESPONSE
3 f
×
where I
is the load step, t
STEP
STEP
load step, t
is the response time of the con-
RESPONSE
troller, and f
is the closed-loop crossover frequency
CO
of system (see the Compensation Design Guidelines
section).
Setting the Current Limit
The MAX15048/MAX15049 use a valley current-sense
method for current limiting. The valley current-limit
threshold (V
) is internally set at 69mV (typ).
LIM
The voltage drop across the low-side MOSFET due to its
on-resistance is used to sense the inductor current. The
voltage drop (V
) across the low-side MOSFET at
VALLEY
the valley point and at I
is:
LOAD
=
×
V
R
(I
VALLEY
DS(ON)
LOAD(MAX)
R
is the on-resistance of the low-side MOSFET,
DS(ON)
I
is the rated load current, and DI
LOAD
peak inductor current.
The R
of the MOSFET varies with temperature.
DS(ON)
Calculate the R
of the MOSFET at its operating
DS(ON)
junction temperature at full load using its data sheet. To
compensate for this temperature variation, the current-
limit circuitry has a temperature coefficient of 3333ppm/NC.
This allows the valley current-limit threshold (V
track and partially compensate for the increase in the
R
of the synchronous MOSFET with increasing
DS(ON)
temperature.
______________________________________________________________________________________
Triple-Output Buck Controllers
with Tracking/Sequencing
When choosing the n-channel MOSFETs, consider the
total gate charge, R
maximum drain-to-source voltage, and package thermal
impedance. The product of the MOSFET gate charge
and on-resistance is a figure of merit, with a lower num-
ber signifying better performance. Choose MOSFETs that
are optimized for high-frequency switching applications.
The average gate-drive current from the MAX15048/
MAX15049s’ output is proportional to the frequency and
gate charge required to drive the MOSFET. The power
dissipated in the MAX15048/MAX15049 is proportional
to the input voltage and the average drive current (see
the Power Dissipation section).
The MAX15048/MAX15049 use a fixed-frequency, volt-
CO
age-mode control scheme that regulates the output
voltage by differentially comparing the “sampled” out-
is the rise time of the
put voltage against a fixed reference. The subsequent
“error” voltage—that appears at the error-amplifier output
(COMP_)—is compared against an internal ramp voltage
to generate the required duty cycle of the pulse-width
modulator. A 2nd-order lowpass LC filter removes the
switching harmonics and passes the DC component of
the pulse-width-modulated signal to the output. The LC
filter, which has an attenuation slope of -40dB/decade,
introduces 180° out-of-phase shift at frequencies above
the LC resonant frequency. This phase shift, in addi-
tion to the inherent 180° of phase shift of the regulator’s
self-governing (negative) feedback system, poses the
potential for positive feedback. The error amplifier and
its associated circuitry are designed to compensate for
this instability in order to achieve a stable closed-loop
I
P-P
-
)
system.
2
The basic regulator loop consists of a power modula-
tor (comprising the regulator’s pulse-width modulator,
associated circuitry, and LC filter), an output feedback
is the peak-to-
P-P
divider, and an error amplifier. The power modulator has
a DC gain set by V
single zero set by the output inductance (L), the output
capacitance (C
quency zero also exists, which is a function of the output
capacitor’s ESR and ESL, though only taken into account
when using very high-quality filter components and/or
) to
LIM
frequencies of operation.
Power-MOSFET Selection
, power dissipation, the
DS(ON)
Compensation Design Guidelines
/V
, with a double pole and a
IN
RAMP
), and its ESR. A second, higher fre-
OUT
21