IC CTRLR PWM STP-DN TRIPL 32WQFN

MAX15048ETJ+

Manufacturer Part NumberMAX15048ETJ+
DescriptionIC CTRLR PWM STP-DN TRIPL 32WQFN
ManufacturerMaxim Integrated Products
MAX15048ETJ+ datasheet
 


Specifications of MAX15048ETJ+

ApplicationsPower Supply Controller, SequencerVoltage - Supply4.7 V ~ 23 V
Current - Supply6mAOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case32-WQFN Exposed Pad
Number Of Outputs3Output Voltage5 V
Input Voltage4.7 V to 23 VSupply Current6 mA
Switching Frequency200 KHzMounting StyleSMD/SMT
Maximum Operating Temperature+ 85 CMinimum Operating Temperature- 40 C
Lead Free Status / RoHS StatusLead free / RoHS CompliantVoltage - Input-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Page 21
22
Page 22
23
Page 23
24
Page 24
25
Page 25
26
Page 26
27
Page 27
28
Page 28
29
Page 29
30
Page 30
31
Page 26/31

Download datasheet (4Mb)Embed
PrevNext
Triple-Output Buck Controllers
with Tracking/Sequencing
Type III: Compensation when f
CO
As previously indicated, the position of the output capac-
itor’s inherent ESR zero is critical in designing an appro-
priate compensation network. When low-ESR ceramic
output capacitors are used, the ESR zero frequency
(f
) is usually much higher than unity crossover
ZERO, ESR
frequency (f
). In this case, a Type III compensation
CO
network is recommended (see Figure 6a).
As shown in Figure 6b, Type III compensation network
introduces two zeros and three poles into the control
loop. The error amplifier has a low-frequency pole at
the origin, two zeros, and higher frequency poles. The
locations of the zeros and poles should be such that the
phase margin peaks at f
.
CO
Set the ratios of f
-to-f
and f
-to-f
CO
Z
P
f
f
CO
P
=
=
5
f
f
Z
CO
to get approximately 60° of phase margin at f
Whichever technique is used, it is important to place the
two zeros at or below the double pole to avoid the con-
ditional stability issue.
V
C
OUT_
CF
R
R
F
I
R
1
C
I
g
M
R
V
REF
2
Figure 6a. Type III Compensation Network
GAIN
(dB)
4TH ASYMPTOTE
3RD ASYMPTOTE
ωR
C
F
I
5TH ASYMPTOTE
1ST ASYMPTOTE
(ωR
(ωR
C
)
-1
I
F
2ND ASYMPTOTE
(R
R
)
-1
F
I
1ST POLE
1ST ZERO
2ND POLE
2ND ZERO
(AT ORIGIN)
(R
C
)
-1
(R
C
)
-1
F
F
I
I
(R
C
)
-1
I
I
Figure 6b. Type III Compensation Network Response
26
_____________________________________________________________________________________
< f
Use the following procedure to calculate the compensa-
ZERO, ESR
tion network components:
1) Select a crossover frequency, f
2) Calculate the LC double-pole frequency, f
3) Select R
4) Place a zero:
equal to five:
CO
where:
.
CO
5) Calculate C
f
:
C
Note: C
I
C
F
over frequency to unity, e.g. G
1V/V. The total loop gain can be expressed logarithmi-
cally as follows:
COMP
20 log
6) Place a second zero, f
determining R
R
R
I -1
F
7) Place a pole (
C
)
-1
I
CF
ω(rad/s)
3RD POLE
(R
C
)
-1
F
CF
:
CO
f
SW
f
CO
10
1
f
=
LC
2
π ×
L C
×
OUT
R 10kI.
F
1
=
×
f
at 0.75 f
Z1
LC
2
π ×
R
×
C
F
F
1
C
=
F
2
π ×
R
×
0.75 f
×
F
LC
for a target unity-gain crossover frequency,
I
π ×
× ×
×
2
f
L C
V
C
OUT
RAMP
O
C
=
I
V
×
R
IN
F
is derived by setting the total loop gain at cross-
(f
) x G
E/A
CO
20 log
×
2
× π ×
f
×
R
×
C
+
10
CO
F
I
G
MOD(DC)
×
10
2
(
)
× π ×
× ×
2
f
L C
CO
OUT
, at or below f
Z2
:
1
1
R
=
1
2
π ×
f
×
C
Z2
I
1
=
f
) at or below f
P1
π ×
×
2
R
C
I
I
1
=
R
I
2
π ×
f
×
C
ZERO, ESR
I
:
LC
(f
) =
MOD
CO
=
0dB
, thereby
LC
:
ZERO, ESR