ISL6545ACRZ Intersil, ISL6545ACRZ Datasheet - Page 5

• Manufacturer Part Number: ISL6545ACRZ
• Description: IC PWM BUCK BST VM 10DFN
• Manufacturer: Intersil

Specifications of ISL6545ACRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 660kHz
• Duty Cycle: 100%
• Voltage - Supply: 4.5 V ~ 14.4 V
• Buck: Yes
• Boost: Yes
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 10-DFN
• Frequency-max: 660kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Specifications
NOTE:
Functional Pin Description (SOIC, DFN)
VCC (SOIC Pin 5, DFN Pin 6)
This pin provides the bias supply for the ISL6545x, as well
as the lower MOSFET’s gate, and the BOOT voltage for the
upper MOSFET’s gate. An internal 5V regulator will supply
bias if V
BOOT will still be sourced by VCC). Connect a well-
decoupled 5V or 12V supply to this pin.
FB (SOIC Pin 6, DFN Pin 8)
This pin is the inverting input of the internal error amplifier. Use
FB, in combination with the COMP/SD pin, to compensate the
voltage-control feedback loop of the converter. A resistor divider
from the output to GND is used to set the regulation voltage.
GND (SOIC Pin 3, DFN Pin 4)
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available. For the DFN package,
Pin 4 MUST be connected for electrical GND; the metal pad
under the package should also be connected to the GND
plane for thermal conductivity.
PHASE (SOIC Pin 8, DFN Pin 10)
Connect this pin to the source of the upper MOSFET, and
the drain of the lower MOSFET. It is used as the sink for the
UGATE driver, and to monitor the voltage drop across the
lower MOSFET for overcurrent protection. This pin is also
monitored by the adaptive shoot-through protection circuitry
to determine when the upper MOSFET has turned off.
UGATE (SOIC Pin 2, DFN Pin 2)
Connect this pin to the gate of upper MOSFET; it provides
the PWM-controlled gate drive. It is also monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
BOOT (SOIC Pin 1, DFN Pin 1)
This pin provides ground referenced bias voltage to the upper
MOSFET driver. A bootstrap circuit is used to create a voltage
Upper Gate Source Impedance
Upper Gate Sink Impedance
Lower Gate Source Impedance
Lower Gate Sink Impedance
PROTECTION/DISABLE
OCSET Current Source
Disable Threshold (COMP/SD pin)
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
CC
rises above 6.5V (but the LGATE/OCSET and
PARAMETER
5
V
-40°C to +85°C. (Continued)
CC
= 12V, T
R
R
V
SYMBOL
R
R
I
DISABLE
UG-SRCl
UG-SNKl
LG-SRCl
LG-SNKl
OCSET
J
= 0 to +85°C. Boldface limits apply over the operating temperature range,
V
V
V
V
ISL6545C; LGATE/OCSET = 0V
ISL6545I; LGATE/OCSET = 0V
CC
CC
CC
CC
ISL6545, ISL6545A
= 4.25V; I = 50mA
= 4.25V; I = 50mA
= 4.25V; I = 50mA
= 4.25V; I = 50mA
TEST CONDITIONS
suitable to drive an N-channel MOSFET (equal to V
the on-chip BOOT diode voltage drop), with respect to PHASE.
COMP/SD (SOIC Pin 7, DFN Pin 9)
This is a multiplexed pin. During soft-start and normal converter
operation, this pin represents the output of the error amplifier.
Use COMP/SD, in combination with the FB pin, to compensate
the voltage-control feedback loop of the converter.
Pulling COMP/SD low (V
shut-down (disable) the controller, which causes the
oscillator to stop, the LGATE and UGATE outputs to be held
low, and the soft-start circuitry to re-arm. The external
pull-down device will initially need to overcome up to 5mA of
COMP/SD output current. However, once the IC is disabled,
the COMP output will also be disabled, so only a 20µA
current source will continue to draw current.
When the pull-down device is released, the COMP/SD pin
will start to rise, at a rate determined by the 20µA charging
up the capacitance on the COMP/SD pin. When the
COMP/SD pin rises above the V
ISL6545x will begin a new Initialization and soft-start cycle.
LGATE/OCSET (SOIC Pin 4, DFN Pin 5)
Connect this pin to the gate of the lower MOSFET; it provides
the PWM-controlled gate drive (from V
monitored by the adaptive shoot-through protection circuitry to
determine when the lower MOSFET has turned off.
During a short period of time following Power-On Reset
(POR) or shut-down release, this pin is also used to
determine the overcurrent threshold of the converter.
Connect a resistor (R
“Overcurrent Protection (OCP)” on page 7 for equations. An
overcurrent trip cycles the soft-start function, after two
dummy soft-start time-outs. Some of the text describing the
LGATE function may leave off the OCSET part of the name,
when it is not relevant to the discussion.
N/C (DFN only; Pin 3, Pin 7)
These two pins in the DFN package are No Connect.
OCSET
(Note 7)
0.375
19.5
18.0
MIN
DISABLE
) from this pin to GND. See
DISABLE
0.400
TYP
2.75
21.5
21.5
3.5
2.7
2.1
= 0.4V nominal) will
CC
). This pin is also
(Note 7)
trip point, the
0.425
MAX
23.5
23.5
CC
March 3, 2011
UNITS
minus
FN6305.6
µA
µA
Ω
Ω
Ω
Ω
V