LM5642XMT/NOPB National Semiconductor, LM5642XMT/NOPB Datasheet - Page 20

• Manufacturer Part Number: LM5642XMT/NOPB
• Description: IC CONV SYNC DUAL BUCK 28-TSSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Step-Down (Buck)r

Specifications of LM5642XMT/NOPB

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 1.3 ~ 35 V
• Current - Output: 20A
• Frequency - Switching: 375kHz
• Voltage - Input: 4.5 ~ 36 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Power - Output: 1.1W
• For Use With: LM5642EVAL-KIT - BOARD EVALUATION LM5642
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM5642XMT; *LM5642XMT/NOPB; LM5642XMT

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will be highest under these circumstances. The input RMS
current in this case is given by:
Where, again, I1 and I2 are the maximum load currents of
channel 1 and 2, and D1 and D2 are the duty cycles. This
equation should be used when both duty cycles are expected
to be higher than 50%.
If the LM5642 is being used with an external clock frequency
other than 200kHz, or 375 kHz for the LM5642X, the preced-
ing equations for input rms current can still be used. The
selection of the first equation or the second changes because
overlap can now occur at duty cycles that are less than 50%.
From the External Frequency Sync section, the maximum du-
ty cycle that ensures no overlap between duty cycles (and
hence input current pulses) is:
There are now three distinct possibilities which must be con-
sidered when selecting the equation for input rms current. The
following applies for the LM5642, and also the LM5642X by
replacing 200 kHz with 375 kHz:
1.
2.
3.
Input capacitors must meet the minimum requirements of
voltage and ripple current capacity. The size of the capacitor
should then be selected based on hold up time requirements.
Bench testing for individual applications is still the best way
to determine a reliable input capacitor value. Input capacitors
should always be placed as close as possible to the current
sense resistor or the drain of the top FET. When high ESR
capacitors such as tantalum are used, a 1µF ceramic capac-
itor should be added as closely as possible to the high-side
FET drain and low-side FET source.
MOSFET Selection
BOTTOM FET SELECTION
During normal operation, the bottom FET is switching on and
off at almost zero voltage. Therefore, only conduction losses
are present in the bottom FET. The most important parameter
when selecting the bottom FET is the on-resistance (R
ON
The bottom FET power loss peaks at maximum input voltage
and load current. The equation for the maximum allowed on-
resistance at room temperature for a given FET package, is:
). The lower the on-resistance, the lower the power loss.
Both duty cycles D
case, the first, simple equation can always be used.
One duty cycle is greater than D
cycle is less than D
can take advantage of the fact that the sync feature
reduces D
other channel. For F
D
> 200kHz, D
(1-D
lower duty cycle, and the channel that has been
increased for the higher duty cycle, the first, simple rms
input current equation can be used.
Both duty cycles are greater than D
identical to a system at 200 kHz where either duty cycle
is 50% or greater. Some overlap of duty cycles is
guaranteed, and hence the second, more complicated
rms input current equation must be used.
MAX
MAX
while D
). By using the channel reduced to D
D
MAX
MAX
2
2
is reduced to D
for one channel, but lengthens it for the
actually increases to (1-D
= F
1
MAX
SYNC
and D
SYNC
. In this case, the system designer
*
2.5 x 10
< 200kHz, D
2
are less than D
MAX
MAX
-6
while D
MAX
and the other duty
1
. This case is
is reduced to
MAX
1
increases to
MAX
). For F
MAX
. In this
for the
SYNC
(23)
(24)
DS-
20
where Tj_max is the maximum allowed junction temperature
in the FET, Ta_max is the maximum ambient temperature,
R
and TC is the temperature coefficient of the on-resistance
which is typically in the range of 4000ppm/°C.
If the calculated R
available, multiple FETs can be used in parallel. This effec-
tively reduces the I
ducing R
calculated R
FET. In the case of three FETs, multiply by 9.
If the selected FET has an Rds value higher than 35.3Ω, then
two FETs with an R
be used in parallel. In this case, the temperature rise on each
FET will not go to Tj_max because each FET is now dissi-
pating only half of the total power.
TOP FET SELECTION
The top FET has two types of losses: switching loss and con-
duction loss. The switching losses mainly consist of crossover
loss and losses related to the low-side FET body diode re-
verse recovery. Since it is rather difficult to estimate the
switching loss, a general starting point is to allot 60% of the
top FET thermal capacity to switching losses. The best way
to precisely determine switching losses is through bench test-
ing. The equation for calculating the on resistance of the top
FET is thus:
Example: Tj_max = 100°C, Ta_max = 60°C, Rqja = 60°C/W,
Vin_min = 5.5V, Vnom = 5V, and Iload_max = 3.6A.
When using FETs in parallel, the same guidelines apply to the
top FET as apply to the bottom FET.
θja
is the junction-to-ambient thermal resistance of the FET,
DS-ON
DS-ON (MAX)
. When using two FETs in parallel, multiply the
DS-ON (MAX)
DS-ON
max
by 4 to obtain the R
term in the above equation, thus re-
less than 141 mΩ (4 x 35.3 mΩ) can
is smaller than the lowest value
DS-ON (MAX)
for each
(25)
(26)
(27)
(28)