ADP3290JCPZ-RL ON Semiconductor, ADP3290JCPZ-RL Datasheet - Page 11

• Manufacturer Part Number: ADP3290JCPZ-RL
• Description: IC CTLR BUCK SW REG 40-LFCSP
• Manufacturer: ON Semiconductor
• Type: Step-Down (Buck)r

Specifications of ADP3290JCPZ-RL

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 4
• Voltage - Output: 0.5 ~ 1.6 V
• Frequency - Switching: 250kHz ~ 4MHz
• Voltage - Input: 12V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Output Voltage: 0.5 V to 1.6 V
• Output Current: 500 uA
• Input Voltage: - 0.3 V to + 6.3 V
• Supply Current: 25 mA
• Switching Frequency: 450 kHz
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Voltage Control Mode
used for the voltage mode control loop. The control input
voltage to the positive input is set via the VID logic
according to the voltages listed.
positioning of the output voltage as a function of current,
commonly known as active voltage positioning. The output
of the amplifier is the COMP pin, which sets the termination
voltage for the internal PWM ramps.
with Resistor R
output voltage at this point. A current source from the FB pin
flowing through R
voltage from the VID voltage. The no load voltage is
negative with respect to the VID DAC. The main loop
compensation is incorporated into the feedback network
between FB and COMP.
Fast Enhanced Transient Modes
for both load steps and load release. For load steps, it senses
the error amp to determine if a load step has occurred and
sequences the proper number of phases on to ramp up the
output current.
load release information to trigger the TRDET pin, which is
then used to adjust the feedback for optimal positioning
especially during high frequency load steps.
ensure proper sequencing and balancing of phases during
high frequency load steps as well as minimizing stress on the
components such as the input filter and MOSFETs.
Delay Timer
with a capacitor from the DELAY pin to ground. In UVLO,
or when EN is logic low, the DELAY pin is held at ground.
After the UVLO and EN signals are asserted, the first delay
time (TD1 in Figure 5) is initiated. A 15 mA current flows out
of the DELAY pin to charge C
the DELAY voltage with a threshold of 1.7 V. The delay time
is therefore set by the 15 mA charging a capacitor from 0 V
to 1.7 V. This DELAY pin is used for multiple delay timings
(TD1, TD3, and TD5) during the startup sequence. Also,
DELAY is used for timing the current limit latchoff, as
explained in the Current Limit, Short−Circuit, and Latchoff
Protection section.
Soft−Start
capacitor from the SS pin to ground. After TD1 and the
phase detection cycle have been completed, the SS time
(TD2 in Figure 5) starts. The SS pin is disconnected from
A high gain, bandwidth voltage mode error amplifier is
This voltage is also offset by the droop voltage for active
The negative input (FB) is tied to the output sense location
The ADP3290 incorporates enhanced transient response
For load release, it also senses the error amp and uses the
Additional information is used during load transients to
The delay times for the startup timing sequence are set
The soft−start times for the output voltage are set with a
B
and is used for sensing and controlling the
B
is used for setting the no load offset
DLY
. A comparator monitors
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GND, and the capacitor is charged up to the 1.1 V boot
voltage by the SS amplifier, which has a limited output
current of 15 mA. The voltage at the FB pin follows the
ramping voltage on the SS pin, limiting the inrush current
during startup. The soft−start time depends on the value of
the boot voltage and C
the boot voltage delay time (TD3 in Figure 5) is started. The
end of the boot voltage delay time signals the beginning of the
second soft−start time (TD4 in Figure 5). The SS voltage now
changes from the boot voltage to the programmed VID DAC
voltage (either higher or lower) using the SS amplifier with
the limited 15 mA output current. The voltage of the FB pin
follows the ramping voltage of the SS pin, limiting the inrush
current during the transition from the boot voltage to the final
DAC voltage. The second soft−start time depends on the boot
voltage, the programmed VID DAC voltage, and C
slew−rate of DVID steps. The current source is changed to
75 mA and the DVID slew−rate becomes 5 X the soft−start
slew−rate. Typically, the SS slew−rate is 2 mV/mS, so the
DVID becomes 10 mV/mS.
and SS are reset to ground to be ready for another soft−start
cycle. Figure 6 shows typical startup waveforms for the
ADP3290.
Once the SS voltage is within 100 mV of the boot voltage,
Once TD5 has finished, the SS pin is then used to limit the
If EN is taken low or if V
1-Vo, 2-EN, 3-SS, 4-DELAY, D0−D3-PWM1~4
Figure 6. Typical Startup Waveform
SS
.
CC
drops below UVLO, DELAY
SS
.