ADP3290JCPZ-RL ON Semiconductor, ADP3290JCPZ-RL Datasheet - Page 21

• Manufacturer Part Number: ADP3290JCPZ-RL
• Description: IC CTLR BUCK SW REG 40-LFCSP
• Manufacturer: ON Semiconductor
• Type: Step-Down (Buck)r

Specifications of ADP3290JCPZ-RL

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 4
• Voltage - Output: 0.5 ~ 1.6 V
• Frequency - Switching: 250kHz ~ 4MHz
• Voltage - Input: 12V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Output Voltage: 0.5 V to 1.6 V
• Output Current: 500 uA
• Input Voltage: - 0.3 V to + 6.3 V
• Supply Current: 25 mA
• Switching Frequency: 450 kHz
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Here, I
maximum signal level that the CSA responds to.
values to reduce the noise and parasitic susceptibility of the
feedback path.
minimum values for the resistors, the following equations result:
ability to select different load lines. Figure 11 shows an
optional MOSFET switch that allows this feature. Here,
design for R
use Equation 14 to set R
LLSET directly to CSCOMP; the R
are not needed.
Output Offset
output voltage of the regulator be offset to a value lower than
the nominal voltage corresponding to the VID code. The
offset is set by a constant current source flowing out of the
FB pin (I
be found using Equation 18.
typically recommended by Intel for various processors and
platforms. Use some simple design guidelines to determine
the requirements. These guidelines are based on having both
bulk capacitors and ceramic capacitors in the system.
is based on the number and type of capacitor to be used. The
best location for ceramic capacitors is inside the socket, with
12 to 18, 1206 size being the physical limit. Other capacitors
can be placed along the outer edge of the socket as well.
It is best to select the resistor values to minimize their
By combining Equation 14 with Equation 15 and selecting
Another useful feature for some VR applications is the
For this design, R
The Intel specification requires that at no load the nominal
The closest standard 1% resistor value is 1.21 kW.
The required output decoupling for the regulator is
First, select the total amount of ceramic capacitance. This
LIM
FB
) and flowing through R
CSA
is the current limit current, which is the
R
R
R
R
= R
LL2
LL1
B
B
+
+
O(MAX)
CSA
+
+
V
1.4 V * 1.381 V
I
O
LIM
VID
= R
R
50 mA
= R
R
CSA
* V
I
15 mA
O
FB
(selected with Q
O
O(MIN)
R
= 1 mW. As a result, connect
* 1
ONL
O
(selected with Q
B
LL1
. The value of R
+ 1.27 kW
R
and R
LL2
LL
LL2
on) and then
resistors
(eq. 18)
(eq. 16)
(eq. 17)
LL
http://onsemi.com
B
off).
can
21
capacitance required, start with a worst case load step
occurring right after a switching cycle has stopped. The
ceramic capacitance then delivers the charge to the load
while the load is ramping up and until the VR has responded
with the next switching cycle.
determining the minimum ceramic capacitance. Due to the
complexity of the PCB parasitics and bulk capacitors, the
actual amount of ceramic capacitance required can vary.
or 22 mF capacitors. For this example, Equation 19 yields
180.8 mF, so eighteen, 22 mF ceramic capacitors suffice.
of bulk capacitance (C
OTF voltage stepping of the output (voltage step V
t
release for a given maximum load step (DI
maximum allowable overshoot. The total amount of load
release voltage is given as DV
DV
response, the ESR of the bulk capacitor bank (R
less than two times the droop resistance (R
is larger than C
OTF specification and can require the use of a smaller
inductor or more phases (and may have to increase the
switching frequency to keep the output ripple the same).
(C
233.75 ms with a settling error of 5 mV. The maximum
allowable load release overshoot for this example is 50 mV,
therefore, solving for the bulk capacitance yields.
V
To determine the minimum amount of ceramic
Equation 19 gives the designer a rough approximation for
The typical ceramic capacitors consist of multiple 10 mF
Next, there is an upper limit imposed on the total amount
A lower limit is based on meeting the capacitance for load
To meet the conditions of these equations and transient
This example uses 18, 22 mF 1206 MLC capacitors
Z
with error of V
C
nK
C
rl
= 396 mF). The VID OTF step change is 1.1V in
X(MAX)
Z(MIN)
is the maximum allowable overshoot voltage.
2
L
R
where : K + * 1n
2
O
w 1
v
V
V
R
VID
V
O
X(MAX)
ERR
).
f
SW
X
1
, the system cannot meet the VID
) when the user considers the VID
1 ) t
V
V
ERR
V
1
n * D *
O
V
= DI
V
V
VID
V
O
× R
2 S
nKR
D I
O
L
O
). If the C
O
R
O
+ DV
X
2
) should be
* 1 * C
O
V
) and a
rl
(eq. 19)
(eq. 20)
, where
in time
X(MIN)
Z