ADP3290JCPZ-RL ON Semiconductor, ADP3290JCPZ-RL Datasheet - Page 24

• Manufacturer Part Number: ADP3290JCPZ-RL
• Description: IC CTLR BUCK SW REG 40-LFCSP
• Manufacturer: ON Semiconductor
• Type: Step-Down (Buck)r

Specifications of ADP3290JCPZ-RL

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 4
• Voltage - Output: 0.5 ~ 1.6 V
• Frequency - Switching: 250kHz ~ 4MHz
• Voltage - Input: 12V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Output Voltage: 0.5 V to 1.6 V
• Output Current: 500 uA
• Input Voltage: - 0.3 V to + 6.3 V
• Supply Current: 25 mA
• Switching Frequency: 450 kHz
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Current Limit Setpoint
value for R
is set with a constant current source (I
flowing out of the I
across R
current limit. R
output. The peak average current is the dc current limit plus
the output ripple current. In this example, choose
I
of 10 A gives an I
in this example, R
THCBR1290−221−R). This results in an R
which 7.5 kW is chosen as the nearest 1% value.
during a load step are determined by:
(V
(V
is 0.433 and the peak current is 46.4 A.
during the secondary current limit is determined by:
(A
an R
results in a per−phase peak current limit of 93.3 A. This
current level can be reached only with an absolute short at
the output, and the current limit latchoff function shuts down
the regulator before overheating can occur.
First, compute the time constants for all the poles and zeros in the system using Equation 38 to Equation 42.
R
R
T
T
R
LIM_DC
A
B
E
E
To select the current limit setpoint, first find the resistor
Here, I
The per−phase initial duty cycle limit and peak current
For the ADP3290, the maximum COMP voltage
The limit of the peak per−phase current described earlier
For the ADP3290, the current balancing amplifier gain
LIM
COMP(MAX)
BIAS
D
+ C
+ R
+ n
+ 4
) is 5 and the clamped COMP pin voltage is 3.3 V. Using
DS(MAX)
+
) is 1.2 V. In this example, the maximum duty cycle
X
X
V
=150 A (130% * TDC ) and having a ripple current
LIM
LIM
I
ILIM
) R
LIM
LIM
R
1 mW ) 5
I
I
D
PHMAX
PHLIM
O
. Thus, increasing R
R
is the peak average current limit for the supply
MAX
of 4.5 mW (low−side on resistance at 150°C)
+
. The current limit threshold for the ADP3290
) is 4.4 V and the COMP pin bias voltage
) A
O
1
LIM
* R
* R
I
LIM
LIM
+ D
4
3
+
PH
D
LIM
+
can be found using:
O
1
V
is 68.1 kW, DCR is 0.57 mW (Delta
V
of 160 A. R
D
COMP(CLAMPED)
f
)
R
pin, which sets up a voltage (V
R
REF
MAX
SW
5.25 mW )
DS
CS
V
R
C
A
L
COMP(MAX)
X
O
X
D
)
+ 0.6 mW ) 0.5 mW * 1 mW
R
R
DCR
V
PH
R
L
R
IN
V
CS
O
V
DS(MAX)
LIM
VID
* V
R
RT
* R
0.57 mW
L
V
X
is selected as 110 kW
* V
* V
RT
R
now increases the
VID
1
REF
)
ILIM
LIM
+ 4.48 mF
BIAS
BIAS
1.4 V
2
= 7.4 kW, for
= 4/3*I
n
0.862 V
L
(eq. 33)
(eq. 34)
(eq. 35)
(eq. 36)
C
http://onsemi.com
( 1 * n
X
REF
LIM
)
1 mW * 0.5 mW )
)
)
R
2
O
24
D )
4
220 nH
4.48 mf + 448 ns
V
I
should represent the load condition within the whole load
current range. The formula below will result R
for I
V
R
4.99 kW is chosen as the nearest 1% value.
order to filter output current ripple. The time constant of
R
switching period. In this example, C
Feedback Loop Compensation Design
possible response of the regulator output to a load change. The
basis for determining the optimum compensation is to make
the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and equal to the droop
resistance (R
output voltage droops in proportion to the load current at any
load current slew rate. This ensures optimal positioning and
minimizes the output decoupling.
ADP3290, the feedback compensation must be set to make
the converter output impedance work in parallel with the
output decoupling to make the load look entirely resistive.
Compensation is needed for several poles and zeros created
by the output inductor and the decoupling capacitors (output
filter).
adequate for proper compensation of the output filter.
Equation 38 to Equation42 are intended to yield an optimal
starting point for the design; some adjustments may be
necessary to account for PCB and component parasitic
effects (see the Tuning the ADP3290 section).
MON
VID
LIM
IMON
IMON
According to the function definition, I
Here, I
There is a capacitor (C
Optimized compensation of the ADP3290 allows the best
Because of the multi−mode feedback structure of the
A type−three compensator on the voltage feedback is
4.48 mF
V
MON
RT
Setpoint
= 7.5 kW, R
* C
is selected as 0.8V when I
. Since I
L
( 1 * 0.467 )
is the total load current, M =10 is the current gain
IMON
O
R
250 pH
1 mW
). With the resistive output impedance, the
IMON
1 mW
should be much bigger (> 10 x) than circuit
MON
IMON
+
output clamp voltage is around 1.1 V,
V
I
1.4 V
1 mW * 0.5 mW
IMON
IMON
0.862 V
is calculated as 5 kW, for which
IMON
0.6 mW
+
) in parallel with R
V
M
+ 38.7 mW
IMON
IMON
L
= I
R
MAX
O
MON
is selected as 0.1 mF.
+ 2.45 ms
R
LIM
I
(130A). While
L
output voltage
IMON
IMON
(eq. 38)
in need:
(eq. 39)
(eq. 40)
(eq. 37)
, in