ISL6530EVAL2

Manufacturer Part NumberISL6530EVAL2
DescriptionEVALUATION BOARD 2 ISL6530
ManufacturerIntersil
ISL6530EVAL2 datasheet
 


Specifications of ISL6530EVAL2

Main PurposeSpecial Purpose DC/DC, DDR Memory SupplyOutputs And Type2, Non-Isolated
Power - Output31.25WVoltage - Output2.5V, 1.25V
Current - Output10A, 5AVoltage - Input4.5 ~ 5.5V
Regulator TopologyBuckFrequency - Switching300kHz
Board TypeFully PopulatedUtilized Ic / PartISL6530
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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(1V/DIV)
0V
T0
T1
T2
TIME
FIGURE 2. SOFT-START INTERVAL
Shoot-Through Protection
A shoot-through condition occurs when both the upper
MOSFET and lower MOSFET are turned on simultaneously,
effectively shorting the input voltage to ground. To protect
the regulators from a shoot-through condition, the ISL6530
incorporates specialized circuitry which insures that
complementary MOSFETs are not ON simultaneously.
The adaptive shoot-through protection utilized by the V
regulator looks at the lower gate drive pin, LGATE1, and the
phase node, PHASE1, to determine whether a MOSFET is
ON or OFF. If PHASE1 is below 0.8V, the upper gate is
defined as being OFF. Similarly, if LGATE1 is below 0.8V, the
lower MOSFET is defined as being OFF. This method of
shoot-through protection allows the V
source current only.
Due to the necessity of sinking current, the V
employs a modified protection scheme from that of the
V
regulator. If the voltage from UGATE2 or from
DDQ
LGATE2 to GND is less than 0.8V, then the respective
MOSFET is defined as being OFF and the other MOSFET is
turned ON.
Since the voltage of the lower MOSFET gates and the upper
MOSFET gate of the V
supply are being measured to
TT
determine the state of the MOSFET, the designer is
encouraged to consider the repercussions of introducing
external components between the gate drivers and their
respective MOSFET gates before actually implementing
such measures. Doing so may interfere with the shoot-
through protection.
Power Down Mode
DDRAM systems include a sleep state in which the V
voltage to the memories is maintained, but signaling is
suspended. During this mode the V
TT
no longer needed. The only load placed on the V
the leakage of the associated signal pins of the DDRAM and
memory controller ICs.
8
ISL6530
When the V2_SD input of the ISL6530 is driven high, the
V
regulator is placed into a “sleep” state. In the sleep
TT
state the main V
VCC (5V)
upper and lower MOSFETs being turned off. The V
is maintained at close to .5xVdd via a low current window
regulator which drives V
Maintaining V
V
(2.5V)
DDQ
and enables rapid wake-up from sleep mode without the
need of softstarting the V
down mode, PGOOD is held LOW.
V
(1.25V)
TT
Output Voltage Selection
The output voltage of the V
programmed to any level between V
internal reference, 0.8V. An external resistor divider is used
to scale the output voltage relative to the reference voltage
and feed it back to the inverting input of the error amplifier,
see Figure 3. However, since the value of R1 affects the
values of the rest of the compensation components, it is
advisable to keep its value less than 5kΩ. R4 can be
calculated based on the following equation:
R4
=
If the output voltage desired is 0.8V, simply route VOUT1
back to the FB pin through R1, but do not populate R4.
DDQ
regulator to
DDQ
regulator
TT
FIGURE 3. OUTPUT VOLTAGE SELECTION OF V
V
TT
DDQ
The ISL6530 allows the designer to bypass the internal 50%
tracking of V
termination voltage is
ISL6530 was designed to divide down the V
bus is
TT
50% through two internal matched resistances. These
resistances are typically 200kΩ.
regulator is disabled, with both the
TT
via the SENSE2 pin.
TT
at .5xV
consumes negligible power
TT
DDQ
regulator. During this power
TT
regulator can be
DDQ
(i.e. +5V) and the
IN
×
R1 0.8V
------------------------------------- -
V
0.8V
OUT1
+5V
D1
VCC
BOOT1
C4
Q1
UGATE1
L
OUT
PHASE1
ISL6530
Q2
+
LGATE1
C
OUT1
FB1
C1
R1
COMP1
C3
C2
R2
R4
Reference Overdrive
that is used as the reference for V
DDQ
bus
TT
V
DDQ
R3
DDQ
. The
TT
voltage by
DDQ
FN9052.2
November 15, 2004