C8051F020-TB Silicon Laboratories Inc, C8051F020-TB Datasheet - Page 170

BOARD PROTOTYPING W/C8051F020

C8051F020-TB

Manufacturer Part Number
C8051F020-TB
Description
BOARD PROTOTYPING W/C8051F020
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F020-TB

Contents
Board
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F020
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
C8051F020/1/2/3
170
Bit7:
Bit6:
Bits5-3:
Bit2:
Bit1:
Bit0:
CP0E
R/W
Bit7
CP0E: Comparator 0 Output Enable Bit.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
ECI0E: PCA0 External Counter Input Enable Bit.
0: PCA0 External Counter Input unavailable at Port pin.
1: PCA0 External Counter Input (ECI0) routed to Port pin.
PCA0ME: PCA0 Module I/O Enable Bits.
000: All PCA0 I/O unavailable at Port pins.
001: CEX0 routed to Port pin.
010: CEX0, CEX1 routed to 2 Port pins.
011: CEX0, CEX1, and CEX2 routed to 3 Port pins.
100: CEX0, CEX1, CEX2, and CEX3 routed to 4 Port pins.
101: CEX0, CEX1, CEX2, CEX3, and CEX4 routed to 5 Port pins.
110: RESERVED
111: RESERVED
UART0EN: UART0 I/O Enable Bit.
0: UART0 I/O unavailable at Port pins.
1: UART0 TX routed to P0.0, and RX routed to P0.1.
SPI0EN: SPI0 Bus I/O Enable Bit.
0: SPI0 I/O unavailable at Port pins.
1: SPI0 SCK, MISO, MOSI, and NSS routed to 4 Port pins.
SMB0EN: SMBus0 Bus I/O Enable Bit.
0: SMBus0 I/O unavailable at Port pins.
1: SMBus0 SDA and SCL routed to 2 Port pins.
ECI0E
R/W
Bit6
Figure 17.7. XBR0: Port I/O Crossbar Register 0
R/W
Bit5
PCA0ME
R/W
Bit4
Rev. 1.4
R/W
Bit3
UART0EN
R/W
Bit2
SPI0EN
R/W
Bit1
SMB0EN 00000000
R/W
Bit0
SFR Address:
Reset Value
0xE1

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