C8051F020-TB Silicon Laboratories Inc, C8051F020-TB Datasheet - Page 267

BOARD PROTOTYPING W/C8051F020

C8051F020-TB

Manufacturer Part Number
C8051F020-TB
Description
BOARD PROTOTYPING W/C8051F020
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F020-TB

Contents
Board
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F020
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
24.1.1. EXTEST Instruction
The EXTEST instruction is accessed via the IR. The Boundary DR provides control and observability of all the
device pins as well as the Weak Pullup feature. All inputs to on-chip logic are set to logic 1.
24.1.2. SAMPLE Instruction
The SAMPLE instruction is accessed via the IR. The Boundary DR provides observability and presetting of the scan-
path latches.
24.1.3. BYPASS Instruction
The BYPASS instruction is accessed via the IR. It provides access to the standard JTAG Bypass data register.
24.1.4. IDCODE Instruction
The IDCODE instruction is accessed via the IR. It provides access to the 32-bit Device ID register.
118, 120, 122, 124,
119, 121, 123, 125,
126, 128, 130, 132
127, 129, 131, 133
Version = 0000b
Part Number = 0000 0000 0000 0011b (C8051F020/1/2/3)
Manufacturer ID = 0010 0100 001b (Silicon Labs)
Bit31
Bit
Version
Bit28 Bit27
Action
Capture
Update
Capture
Update
Figure 24.2. DEVICEID: JTAG Device ID Register
Table 24.1. Boundary Data Register Bit Definitions
Part Number
Target
P7.n output enable from MCU
P7.n output enable to pin
P7.n input from pin
P7.n output to pin
Bit12 Bit11
Rev. 1.4
Manufacturer ID
C8051F020/1/2/3
Bit1
Bit0
1
0xn0003243
Reset Value
267

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