C8051F020-TB Silicon Laboratories Inc, C8051F020-TB Datasheet - Page 190

• Manufacturer Part Number: C8051F020-TB
• Description: BOARD PROTOTYPING W/C8051F020
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020-TB

• Contents: Board
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F020
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F020/1/2/3
Setting the SMBus0 Free Timer Enable bit (FTE, SMB0CN.1) to logic 1 enables the timer in SMB0CR. When SCL
goes high, the timer in SMB0CR counts up. A timer overflow indicates a free bus timeout: if SMBus0 is waiting to
generate a START, it will do so after this timeout. The bus free period should be less than 50 µs (see Figure 18.9,
SMBus0 Clock Rate Register).
When the TOE bit in SMB0CN is set to logic 1, Timer 3 is used to detect SCL low timeouts. If Timer 3 is enabled
(see
Section “22.2. Timer 3” on page
240), Timer 3 is forced to reload when SCL is high, and forced to count when
SCL is low. With Timer 3 enabled and configured to overflow after 25 ms (and TOE set), a Timer 3 overflow indi-
cates a SCL low timeout; the Timer 3 interrupt service routine can then be used to reset SMBus0 communication in
the event of an SCL low timeout.
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