C8051F020-TB Silicon Laboratories Inc, C8051F020-TB Datasheet - Page 198

• Manufacturer Part Number: C8051F020-TB
• Description: BOARD PROTOTYPING W/C8051F020
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020-TB

• Contents: Board
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F020
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F020/1/2/3
19.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
19.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to
serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master, and an
input when SPI0 is operating as a slave. Data is transferred most-significant bit first.
19.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is used
to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a master, and an
output when SPI0 is operating as a slave. Data is transferred most-significant bit first. A SPI slave places the MISO
pin in a high-impedance state when the slave is not selected.
19.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used to synchro-
nize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 generates this signal when
operating as a master.
19.1.4. Slave Select (NSS)
The slave select (NSS) signal is an input used to select SPI0 as a slave, or to disable SPI0 as a master. Note that the
NSS signal is always an input to SPI0; with SPI0 operating as a master, slave select signals must be output via general
purpose port I/O pins. See Figure 19.2 for a typical configuration; see Section
ority Crossbar
The NSS signal must be low to initiate a transfer with SPI0 as a slave; SPI0 will exit slave mode when NSS is
released high. Note that received data is not latched into the receive buffer until NSS is high. For multiple-byte trans-
fers, NSS must be released high for at least 4 system clocks following each byte that is received by the SPI0 slave.
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Decoder” on page
Master
Device
GPIO
MISO
MOSI
SCK
Figure 19.2. Typical SPI Interconnection
163
for general purpose port configuration.
Device
Slave
NSS
Rev. 1.4
Device
Slave
NSS
Device
“17.1. Ports 0 through 3 and the Pri-
Slave
NSS
VDD
MISO
MOSI
SCK