AD9517-2/PCBZ Analog Devices Inc, AD9517-2/PCBZ Datasheet - Page 47

• Manufacturer Part Number: AD9517-2/PCBZ
• Description: BOARD EVAL FOR AD9517-2
• Manufacturer: Analog Devices Inc

Specifications of AD9517-2/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9517-2
• Primary Attributes: 2 Inputs, 12 Outputs, 2.2GHz VCO
• Secondary Attributes: CMOS, LVDS, LVPECL Output Logic, ADIsimCLK™ Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IINPUT TO CHANNEL DIVIDER
A SYNC operation brings all outputs that have not been
excluded (by the nosync bit) to a preset condition before
allowing the outputs to begin clocking in synchronicity. The
preset condition takes into account the settings in each of the
channel’s start high bit and its phase offset. These settings
govern both the static state of each output when the SYNC
operation is happening and the state and relative phase of the
outputs when they begin clocking again upon completion of the
SYNC operation. Between outputs and after synchronization,
this allows for the setting of phase offsets.
The AD9517 outputs are in pairs, sharing a channel divider per
pair (two pairs of pairs, four outputs, in the case of CMOS). The
synchronization conditions apply to both outputs of a pair.
SYNC PIN
SYNC PIN
INPUT TO CHANNEL DIVIDER
INPUT TO VCO DIVIDER
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
CHANNEL DIVIDER
INPUT TO CLK
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT OF
OUTPUT OF
Figure 56. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input
Figure 57. SYNC Timing When VCO Divider Is Not Used—CLK Input Only
1
1
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
2
2
3
3
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER OUTPUT STATIC
4
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4
5
5
6
6
Each channel (a divider and its outputs) can be excluded from
any SYNC operation by setting the nosync bit of the channel.
Channels that are set to ignore SYNC (excluded channels) do
not set their outputs static during a SYNC operation, and their
outputs are not synchronized with those of the nonexcluded
channels.
Clock Outputs
The AD9517 offers three output level choices: LVPECL, LVDS,
and CMOS. OUT0 to OUT3 are LVPECL differential outputs;
and OUT4 to OUT7 are LVDS/CMOS outputs. These outputs
can be configured as either LVDS differential or as pairs of
single-ended CMOS outputs.
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
1
1
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
AD9517-2