PIC18F14K50-I/SS Microchip Technology, PIC18F14K50-I/SS Datasheet - Page 243

• Manufacturer Part Number: PIC18F14K50-I/SS
• Description: IC PIC MCU FLASH 8KX16 20-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F14K50-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244023 - PROC EXTENS PAK PIC18F1XK50DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 20-2:
TABLE 20-3:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SRCON0
SRCON1
CM2CON1
INTCON3
TRISC
Legend: Shaded cells are not used with the comparator voltage reference.
SRSPE
Name
R/W-0
MC1OUT MC2OUT
TRISC7
SRSPE: SR Latch Peripheral Set Enable bit
1 = INT1 pin status sets SR Latch
0 = INT1pin status has no effect on SR Latch
SRSCKE: SR Latch Set Clock Enable bit
1 = Set input of SR latch is pulsed with SRCLK
0 = Set input of SR latch is not pulsed with SRCLK
SRSC2E: SR Latch C2 Set Enable bit
1 = C2 Comparator output sets SR Latch
0 = C2 Comparator output has no effect on SR Latch
SRSC1E: SR Latch C1 Set Enable bit
1 = C1 Comparator output sets SR Latch
0 = C1 Comparator output has no effect on SR Latch
SRRPE: SR Latch Peripheral Reset Enable bit
1 = INT1 pin resets SR Latch
0 = INT1 pin has no effect on SR Latch
SRRCKE: SR Latch Reset Clock Enable bit
1 = Reset input of SR latch is pulsed with SRCLK
0 = Reset input of SR latch is not pulsed with SRCLK
SRRC2E: SR Latch C2 Reset Enable bit
1 = C2 Comparator output resets SR Latch
0 = C2 Comparator output has no effect on SR Latch
SRRC1E: SR Latch C1 Reset Enable bit
1 = C1 Comparator output resets SR Latch
0 = C1 Comparator output has no effect on SR Latch
SRLEN
SRSPE
INT2IP
Bit 7
REGISTERS ASSOCIATED WITH THE SR LATCH
SRSCKE
R/W-0
SRCON1: SR LATCH CONTROL REGISTER 1
SRSCKE
SRCLK2
TRISC6
INT1IP
Bit 6
W = Writable bit
‘1’ = Bit is set
SRSC2E
R/W-0
SRSC2E SRSC1E
SRCLK1
C1RSEL
TRISC5
Bit 5
—
SRSC1E
R/W-0
SRCLK0
C2RSEL
TRISC4
Preliminary
INT2IE
Bit 4
U = Unimplemented
‘0’ = Bit is cleared
TRISC3
SRQEN
SRRPE
C1HYS
SRRPE
INT1IE
R/W-0
Bit 3
SRNQEN
SRRCKE
TRISC2
PIC18F/LF1XK50
C2HYS
Bit 2
SRRCKE
—
R/W-0
SRRC2E
C1SYNC
TRISC1
INT2IF
SRPS
Bit 1
C = Clearable only bit
x = Bit is unknown
SRRC2E
R/W-0
SRRC1E
C2SYNC
TRISC0
INT1IF
SRPR
Bit 0
DS41350E-page 243
SRRC1E
R/W-0
on page
Values
Reset
288
288
288
285
288
bit 0