PIC18F14K50-I/SS Microchip Technology, PIC18F14K50-I/SS Datasheet - Page 263

• Manufacturer Part Number: PIC18F14K50-I/SS
• Description: IC PIC MCU FLASH 8KX16 20-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F14K50-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244023 - PROC EXTENS PAK PIC18F1XK50DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.4.4
An endpoint is defined to have a ping-pong buffer when
it has two sets of BD entries: one set for an Even
transfer and one set for an Odd transfer. This allows the
CPU to process one BD while the SIE is processing the
other BD. Double-buffering BDs in this way allows for
maximum throughput to/from the USB.
The USB module supports four modes of operation:
• No ping-pong support
• Ping-pong buffer support for OUT Endpoint 0 only
• Ping-pong buffer support for all endpoints
• Ping-pong buffer support for all other Endpoints
The ping-pong buffer settings are configured using the
PPB<1:0> bits in the UCFG register.
The USB module keeps track of the Ping-Pong Pointer
individually for each endpoint. All pointers are initially
reset to the Even BD when the module is enabled. After
FIGURE 22-6:
 2010 Microchip Technology Inc.
2FFh
200h
23Fh
except Endpoint 0
Note:
Maximum Memory
Used: 64 bytes
Maximum BDs:
16 (BD0 to BD15)
PPB<1:0> = 00
No Ping-Pong
Data RAM
Available
Buffers
as
PING-PONG BUFFERING
Memory area not shown to scale.
EP0 OUT
Descriptor
EP0 IN
Descriptor
EP1 OUT
Descriptor
EP1 IN
Descriptor
EP7 IN
Descriptor
BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES
2FFh
200h
243h
Ping-Pong Buffer
Maximum Memory
Used: 68 bytes
Maximum BDs:
17 (BD0 to BD16)
PPB<1:0> = 01
on EP0 OUT
Data RAM
Available
as
EP0 OUT Even
Descriptor
EP0 OUT Odd
Descriptor
EP0 IN
Descriptor
EP1 OUT
Descriptor
EP1 IN
Descriptor
EP7 IN
Descriptor
Preliminary
2FFh
27Fh
200h
Ping-Pong Buffers
Maximum Memory
Used: 128 bytes
Maximum BDs:
32 (BD0 to BD31)
PPB<1:0> = 10
on all EPs
the completion of a transaction (UOWN cleared by the
SIE), the pointer is toggled to the Odd BD. After the
completion of the next transaction, the pointer is
toggled back to the Even BD and so on.
The Even/Odd status of the last transaction is stored in
the PPBI bit of the USTAT register. The user can reset
all Ping-Pong Pointers to Even using the PPBRST bit.
Figure 22-6
operation and how USB RAM is filled with the BDs.
BDs have a fixed relationship to a particular endpoint,
depending on the buffering configuration. The mapping
of BDs to endpoints is detailed in
relationship also means that gaps may occur in the
BDT if endpoints are not enabled contiguously. This
theoretically means that the BDs for disabled endpoints
could be used as buffer space. In practice, users
should avoid using such spaces in the BDT unless a
method of validating BD addresses is implemented.
EP0 OUT Even
Descriptor
EP0 OUT Odd
Descriptor
EP0 IN Even
Descriptor
EP0 IN Odd
Descriptor
EP1 OUT Even
Descriptor
EP1 OUT Odd
Descriptor
EP1 IN Even
Descriptor
EP1 IN Odd
Descriptor
EP7 IN Odd
Descriptor
PIC18F/LF1XK50
shows the four different modes of
277h
2FFh
200h
Ping-Pong Buffers
Maximum Memory
Used: 120 bytes
Maximum BDs:
30 (BD0 to BD29)
on all other EPs
PPB<1:0> = 11
Data RAM
Available
except EP0
as
DS41350E-page 263
Table
EP0 OUT
Descriptor
EP0 IN
Descriptor
EP1 OUT Even
Descriptor
EP1 OUT Odd
Descriptor
EP1 IN Odd
Descriptor
EP7 IN Odd
Descriptor
EP1 IN Even
Descriptor
22-2. This