PIC18F14K50-I/SS Microchip Technology, PIC18F14K50-I/SS Datasheet - Page 344

• Manufacturer Part Number: PIC18F14K50-I/SS
• Description: IC PIC MCU FLASH 8KX16 20-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F14K50-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244023 - PROC EXTENS PAK PIC18F1XK50DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F/LF1XK50
SLEEP
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
† If WDT causes wake-up, this bit is cleared.
DS41350E-page 344
Q Cycle Activity:
Before Instruction
After Instruction
Decode
TO =
PD =
TO =
PD =
Q1
?
?
1 †
0
operation
Enter Sleep mode
None
00h  WDT,
0  WDT postscaler,
1  TO,
0  PD
TO, PD
The Power-down Status bit (PD) is
cleared. The Time-out Status bit (TO)
is set. Watchdog Timer and its post-
scaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
1
1
SLEEP
SLEEP
Q2
0000
No
0000
Process
Data
Q3
0000
Sleep
Go to
Q4
0011
Preliminary
SUBFWB
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
Example 3:
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
register ‘f’
0 f 255
d  [0,1]
a  [0,1]
(W) – (f) – (C) dest
N, OV, C, DC, Z
Subtract register ‘f’ and CARRY flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored in
register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f 95 (5Fh). See
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode”
1
1
SUBFWB
SUBFWB
SUBFWB
Subtract f from W with borrow
SUBFWB
Read
Q2
0101
3
2
1
FF
2
0
0
1
2
5
1
2
3
1
0
0
1
2
0
0
2
1
1
0
 2010 Microchip Technology Inc.
; result is negative
; result is positive
; result is zero
for details.
01da
REG, 1, 0
REG, 0, 0
REG, 1, 0
f {,d {,a}}
Process
Data
Q3
Section 25.2.3
ffff
destination
Write to
Q4
ffff