PIC18F14K50-I/SS Microchip Technology, PIC18F14K50-I/SS Datasheet - Page 260

• Manufacturer Part Number: PIC18F14K50-I/SS
• Description: IC PIC MCU FLASH 8KX16 20-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F14K50-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244023 - PROC EXTENS PAK PIC18F1XK50DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F/LF1XK50
The BDnSTAT byte of the BDT should always be the
last byte updated when preparing to arm an endpoint.
The SIE will clear the UOWN bit when a transaction
has completed.
No hardware mechanism exists to block access when
the UOWN bit is set. Thus, unexpected behavior can
occur if the microcontroller attempts to modify memory
when the SIE owns it. Similarly, reading such memory
may produce inaccurate data until the USB peripheral
returns ownership to the microcontroller.
22.4.1.2
When UOWN = 0, the microcontroller core owns the
BD. At this point, the other seven bits of the register
take on control functions.
The
(BDnSTAT<3>), controls data toggle parity checking.
Setting DTSEN enables data toggle synchronization by
the SIE. When enabled, it checks the data packet’s par-
ity against the value of DTS (BDnSTAT<6>). If a packet
arrives with an incorrect synchronization, the data will
essentially be ignored. It will not be written to the USB
RAM and the USB transfer complete interrupt flag will
not be set. The SIE will send an ACK token back to the
host to Acknowledge receipt, however. The effects of
the DTSEN bit on the SIE are summarized in
Table
TABLE 22-1:
DS41350E-page 260
DATA0
DATA1
DATA0
DATA1
Either
Either, with error
Legend: x = don’t care
OUT Packet
from Host
22-1.
Data
BDnSTAT Register (CPU Mode)
Toggle
EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION
Sync
DTSEN
BDnSTAT Settings
1
1
1
1
0
x
Enable
DTS
0
0
1
1
x
x
bit,
DTSEN
Handshake
Preliminary
ACK
ACK
ACK
ACK
ACK
NAK
Device Response after Receiving Packet
UOWN
The Buffer Stall bit, BSTALL (BDnSTAT<2>), provides
support for control transfers, usually one-time stalls on
Endpoint 0. It also provides support for the
SET_FEATURE/CLEAR_FEATURE commands speci-
fied in Chapter 9 of the USB specification; typically,
continuous STALLs to any endpoint other than the
default control endpoint.
The BSTALL bit enables buffer stalls. Setting BSTALL
causes the SIE to return a STALL token to the host if a
received token would use the BD in that location. The
EPSTALL bit in the corresponding UEPn control regis-
ter is set and a STALL interrupt is generated when a
STALL is issued to the host. The UOWN bit remains set
and the BDs are not changed unless a SETUP token is
received. In this case, the STALL condition is cleared
and the ownership of the BD is returned to the
microcontroller core.
The BD<9:8> bits (BDnSTAT<1:0>) store the two Most
Significant digits of the SIE byte count; the lower 8 dig-
its are stored in the corresponding BDnCNT register.
See
information.
0
1
1
0
0
1
Section 22.4.2 “BD Byte Count”
TRNIF
1
0
0
1
1
0
BDnSTAT and USTAT Status
 2010 Microchip Technology Inc.
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