AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 126

• Manufacturer Part Number: AT91RM9200-QU-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QU-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Processor Series: AT91Rx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, UART, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 122
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
• Minimum Operating Temperature: - 40 C
• Eeprom Memory: 0 Bytes
• Input Output: 122
• Interface: EBI/EMI, UART/USART
• Ios: 122
• Memory Type: ROM
• Number Of Bits: 32
• Package Type: 208-pin PQFP
• Programmable Memory: 128K Bytes
• Timers: 3-16-bit
• Voltage, Range: 1.65-1.95 V
• Cpu Family: 91R
• Device Core: ARM920T
• Device Core Size: 32b
• Frequency (max): 180MHz
• Total Internal Ram Size: 16KB
• # I/os (max): 122
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.3.4
126
AT91RM9200
Abort Status
The Remap Command is accessible through the Memory Controller User Interface by writing the
MC_RCR (Remap Control Register) RCB field to one.
The Remap Command can be cancelled by writing the MC_RCR RCB field to one, which acts as
a toggling command. This allows easy debug of the user-defined boot sequence by offering a
simple way to put the chip in the same configuration as just after a reset.
Table 16-1 on page 125
nature of the memory mapped to the address 0x0.
There are two reasons for an abort to occur:
When an abort occurs, a signal is sent back to all the masters, regardless of which one has gen-
erated the access. However, only the master having generated the access leading to the abort
takes this signal into account.
The abort signal generates directly an abort on the ARM9TDMI. Note that, from the processor
perspective, an abort can also be generated by the Memory Management Unit of the ARM920T,
but this is obviously not managed by the Memory Controller and not discussed in this section.
The Peripheral DMA Controller does not handle the abort input signal (and that’s why the con-
nection is not represented in
HcInterruptStatus register and resets its operations. The EMAC reports the Abort to the user
through the ABT bit in its Status Register, which might generate an interrupt.
To facilitate debug or for fault analysis by an operating system, the Memory Controller integrates
an Abort Status register set.
The full 32-bit wide abort address is saved in the Abort Address Status Register (MC_AASR).
Parameters of the access are saved in the Abort Status Register (MC_ASR) and include:
In case of Data Abort from the processor, the address of the data access is stored. This is prob-
ably the most useful, as finding which address has generated the abort would require
disassembling the instruction and full knowledge of the processor context.
However, in case of prefetch abort, the address might have changed, as the prefetch abort is
pipelined in the ARM processor. The ARM processor takes the prefetch abort into account only if
the read instruction is actually executed and it is probable that several aborts have occurred dur-
ing this time. So, in this case, it is preferable to use the content of the Abort Link register of the
ARM processor.
• an access to an undefined address
• an access to a misaligned address.
• the size of the request (ABTSZ field)
• the type of the access, whether it is a data read or write or a code fetch (ABTTYP field)
• whether the access is due to accessing an undefined address (UNDADD bit) or a misaligned
• the source of the access leading to the last abort (MST0, MST1, MST2 and MST3 bits)
• whether or not an abort occurred for each master since the last read of the register
address (MISADD bit)
(SVMST0, SVMST1, SVMST2 and SVMST3 bits) except if it is traced in the MST bits.
is provided to summarize the effect of these two key features on the
Figure
16-1). The UHP reports an unrecoverable error in the
1768I–ATARM–09-Jul-09