AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 221
![IC ARM9 MCU 208 PQFP](/photos/6/73/67311/313-208-pqfp_sml.jpg)
AT91RM9200-QU-002
Manufacturer Part Number
AT91RM9200-QU-002
Description
IC ARM9 MCU 208 PQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91RM9200-EK.pdf
(41 pages)
2.AT91RM9200-QU-002.pdf
(701 pages)
3.AT91RM9200-QU-002.pdf
(38 pages)
Specifications of AT91RM9200-QU-002
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR
Number Of I /o
122
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Processor Series
AT91Rx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, EBI, I2S, SPI, UART, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
122
Number Of Timers
10 bit
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
Minimum Operating Temperature
- 40 C
Eeprom Memory
0 Bytes
Input Output
122
Interface
EBI/EMI, UART/USART
Ios
122
Memory Type
ROM
Number Of Bits
32
Package Type
208-pin PQFP
Programmable Memory
128K Bytes
Timers
3-16-bit
Voltage, Range
1.65-1.95 V
Cpu Family
91R
Device Core
ARM920T
Device Core Size
32b
Frequency (max)
180MHz
Total Internal Ram Size
16KB
# I/os (max)
122
Number Of Timers - General Purpose
6
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
208
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Figure 20-5. Asynchronous Read and Write Accesses with Non-multiplexed Address and Data
20.6.4
20.6.4.1
20.6.4.2
1768I–ATARM–09-Jul-09
BFAVD
D[15:0]
D[15:0]
Burst Flash Controller Synchronous Mode
A[24:0]
Output
BFWE
BFOE
BFCS
BFCK
Input
Burst Read Protocols
Read Access in Burst Mode
Writing the Burst Flash Controller Operating Mode field (BFCOM) to 2
ler Mode Register” on page 227.
BFCK pin. Only read accesses are treated and write accesses are ignored. The BFC supports
read access of bytes, half-words or words.
The BFC supports two burst read protocols:
When a read access is requested in Burst Mode, the requested address is registered in the
BFC. For subsequent read accesses, the address is compared to the previous one. Then the
two following cases are considered:
• Clock Controlled Address Advance, the internal address of the burst Flash is automatically
• Signal Controlled Address Advance, the internal address of the burst Flash is incremented
1. In case of a non-sequential access, the current burst is broken and the BFC launches a
incremented at each BFCK cycle.
only when the BFBAA signal is active.
new burst by performing an address latch cycle. The address is presented on the
address bus in any case and on the data bus if the multiplexed bus option is enabled.
Asynchronous
Read Access
Read Address
AVL
Address Valid Latency = 4 BFCK cycles (AVL field = 3)
Output Enable Latency (OEL) = 1 BFCK cycle
Data
OEL = 1
puts the BFC in Burst Mode. The BFC Clock is driven on the
Asynchronous
Write Access
Write Address
AVL
Data
See “Burst Flash Control-
AT91RM9200
221
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